Recommended
More Related Content
Similar to Peripheral registers and GPIO configuration for STM32 microcontroller
Similar to Peripheral registers and GPIO configuration for STM32 microcontroller (20)
More from mayank272369
More from mayank272369 (20)
Recently uploaded
Recently uploaded (20)
Peripheral registers and GPIO configuration for STM32 microcontroller
- 1. # peripheral registers .equ PWR_BASE0x40007000 .equ PWR_CR0x00 .equ PWR_CR_PMODE0x4000 .equ RCC_BASE0x40023800 .equ RCC_CR0x00 .equ RCC_CR_HSEON0x00010000 .equ RCC_CR_HSERDY0x00020000 .equ RCC_CR_PLLON0x01000000 .equ RCC_CR_PLLRDY0x02000000 .equ RCC_PLLCFGR0x04 .equ PLL_M8 .equ PLL_N336 .equ PLL_P2 .equ PLL_Q7 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ // #define PLL_M 8 // #define PLL_N 336 /* SYSCLK = PLL_VCO / PLL_P */ // #define PLL_P 2 /* USB OTG FS SDIO and RNG Clock = PLL_VCO / PLLQ */ // #define PLL_Q 7 .equ RCC_CFGR0x08 .equ RCC_CFGR_MCO1_MASK0x00600000 .equ RCC_CFGR_MCO1_HSI0x00000000 .equ RCC_CFGR_MCO1_LSI0x00200000 .equ RCC_CFGR_MCO1_HSE0x00400000 .equ RCC_CFGR_MCO1_PLL0x00600000 .equ RCC_CFGR_MCO2_MASK0xC0000000 .equ RCC_CFGR_MCO2_SYSCLK0x00000000 .equ RCC_CFGR_MCO2_PLLI2S0x40000000 .equ RCC_CFGR_MCO2_HSE0x80000000 .equ RCC_CFGR_MCO2_PLL0xC0000000 .equ RCC_CFGR_MCO2_Div_10x00000000 .equ RCC_CFGR_HPRE_DIV10x00000000 .equ RCC_CFGR_PPRE2_DIV20x00008000 .equ RCC_CFGR_PPRE1_DIV40x00001400 .equ RCC_CFGR_SW0x00000003 .equ RCC_CFGR_SW_PLL0x00000002 .equ RCC_CFGR_SWS0x0000000C .equ RCC_CFGR_SWS_PLL0x00000008 .equ RCC_PLLCFGR_PLLSRC_HSE0x00400000 .equ RCC_CIR0x0c .equ RCC_AHB1ENR0x30 .equ RCC_AHB1ENR_GPIOA_EN0x01 .equ RCC_AHB1ENR_GPIOB_EN0x02 .equ
- 2. RCC_AHB1ENR_GPIOC_EN0x04 .equ RCC_AHB1ENR_GPIOD_EN0x08 .equ RCC_AHB1ENR_GPIOE_EN0x10 .equ RCC_APB1ENR0x40 .equ RCC_APB1ENR_PWREN0x10000000 .equ FLASH_BASE0x08000000 .equ FLASH_R_BASE0x40023c00 .equ FLASH_ACR0x00 .equ FLASH_ACR_ICEN0x00000200 .equ FLASH_ACR_DCEN0x00000400 .equ FLASH_ACR_LATENCY_5WS0x00000005 .equ VECT_TAB_OFFSET0x00 .equ SCB_BASE0xE000ED00 .equ SCB_VTOR0x08 .equ GPIOA_BASE0x40020000 .equ GPIOB_BASE0x40020400 .equ GPIOC_BASE0x40020800 .equ GPIOD_BASE0x40020C00 .equ GPIOE_BASE0x40021000 .equ GPIO_MODER0x00 .equ GPIO_MODER_IN0b00 .equ GPIO_MODER_OUT0b01 .equ GPIO_MODER_AF0b10 .equ GPIO_MODER_ANALOG0b11 .equ GPIO_OTYPER0x04 .equ GPIO_OTYPER_PP0b00 .equ GPIO_OTYPER_OD0b01 .equ GPIO_OSPEEDR0x08 .equ GPIO_OSPEEDR_LS0b00 .equ GPIO_OSPEEDR_MS0b01 .equ GPIO_OSPEEDR_FS0b10 .equ GPIO_OSPEEDR_HS0b11 .equ GPIO_PUPDR0x0c .equ GPIO_PUPDR_NOPUP0b00 .equ GPIO_PUPDR_PUP0b01 .equ GPIO_PUPDR_PDOWN0b10 .equ GPIO_IDR0x10 .equ GPIO_ODR0x14 .equ SYST_BASE0xE000E010 .equ SYST_CSR0x0 .equ SYST_RVR0x4 .equ SYST_CVR0x8 .equ SYST_CALIB0xC .equ SYST_RVR_MASK0x00ffffff .equ SYST_CSR_CLKSOURCE0x00000004 .equ SYST_CSR_TICKINT0x00000002 .equ SYST_CSR_ENABLE0x00000001 // file: rcc.s .syntax unified .thumb
- 3. .include "src/periph_regs.inc" .text .align 2 .global rcc_gpio_enable .thumb_func .type rcc_gpio_enable, %function rcc_gpio_enable: mov r3,#4 cmp r0,r3 bgt skip_enable ldr r3,=RCC_BASE ldr r1,[r3, #RCC_AHB1ENR] mov r2,#1 lsl r2,r0 orr r1,r2 str r1,[r3, RCC_AHB1ENR] skip_enable: bx lr .end #define SysTick_BASE (0xE000E010) /*!< SysTick Base Address */ struct SysTick_t *SysTick = (struct SysTick_t*)SysTick_BASE; /*!< SysTick Struct Pointer */ struct SysTick_t
- 4. { /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ int CTRL; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ int LOAD; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ int VAL; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ int CAL; }; unsigned int SysTick_Config(unsigned int ticks) { /* set reload register */ SysTick->LOAD = ticks / 2; /* set reload register - don't allow bigger than 2^24-1! */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = 0b111; /* Clock source is processor clock, Enable SysTick IRQ, and enable SysTick Timer Counter */ return (0); /* Function successful but we won't check */ }
- 5. # file: gpio_regs.inc .equ GPIOA_BASE, 0x40020000 .equ GPIOB_BASE, 0x40020400 .equ GPIOC_BASE, 0x40020800 .equ GPIOD_BASE, 0x40020c00 .equ GPIOE_BASE, 0x40021000 .equ GPIO_MODER, 0x00 .equ GPIO_OTYPER, 0x04 .equ GPIO_OSPEEDR, 0x08 .equ GPIO_PUPDR, 0x0c .equ GPIO_IDR, 0x10 .equ GPIO_ODR, 0x14 .equ GPIO_BSRR, 0x18 .equ GPIO_LCKR, 0x1c .equ GPIO_AFRL, 0x20 .equ GPIO_AFRH, 0x24 # file: SetSysClock.s .syntax unified .thumb .file "SetSysClock.s" .include "src/periph_regs.inc" .text .align 2 .global SetSysClock .thumb_func .type SetSysClock, %function
- 6. SetSysClock: /**************************************************** **************************/ /* PLL (clocked by HSE) used as System clock source */ /**************************************************** **************************/ push {r4,r5,r6,r7,lr} ldr r7,=#RCC_BASE /* Enable HSE */ ldr r4,[r7,#RCC_CR] ldr r5,=#RCC_CR_HSEON orr r4,r5 str r4,[r7,#RCC_CR] /* Wait till HSE is ready and if Time out is reached exit */ ldr r3,=#0x500 Wait_HSE_Ready: subs r3,#1 beq fail_startup ldr r4,[r7,#RCC_CR] ldr r5,=#RCC_CR_HSERDY ands r4,r5 beq Wait_HSE_Ready
- 7. /* Enable high performance mode, System frequency up to 168 MHz */ ldr r4,[r7,#RCC_APB1ENR] ldr r5,=#RCC_APB1ENR_PWREN orr r4,r5 str r4,[r7,#RCC_APB1ENR] ldr r7,=#PWR_BASE ldr r4,[r7,#PWR_CR] ldr r5,=#PWR_CR_PMODE orr r4,r5 str r4,[r7,#PWR_CR] ldr r7,=#RCC_BASE /* HCLK = SYSCLK / 1*/ ldr r4,[r7,#RCC_CFGR] ldr r5,=#RCC_CFGR_HPRE_DIV1 orr r4,r5 str r4,[r7,#RCC_CFGR] /* PCLK2 = HCLK / 2*/ ldr r4,[r7,#RCC_CFGR] ldr r5,=#RCC_CFGR_PPRE2_DIV2 orr r4,r5 str r4,[r7,#RCC_CFGR] /* PCLK1 = HCLK / 4*/ ldr r4,[r7,#RCC_CFGR]
- 8. ldr r5,=#RCC_CFGR_PPRE1_DIV4 orr r4,r5 str r4,[r7,#RCC_CFGR] /* Configure the main PLL */ ldr r4,=#( PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) ) str r4,[r7,#RCC_PLLCFGR] /* Enable the main PLL */ ldr r4,[r7,#RCC_CR] ldr r5,=#RCC_CR_PLLON orr r4,r5 str r4,[r7,#RCC_CR] Wait_PLL_Ready: ldr r4,[r7,#RCC_CR] ldr r5,=#RCC_CR_PLLRDY ands r4,r5 beq Wait_PLL_Ready /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ ldr r7,=#FLASH_R_BASE ldr r4,=#(FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS) str r4,[r7,#FLASH_ACR] ldr r7,=#RCC_BASE /* Select the main PLL as system clock source */
- 9. ldr r4,[r7,#RCC_CFGR] ldr r5,=#~(RCC_CFGR_SW) and r4,r5 str r4,[r7,#RCC_CFGR] ldr r4,[r7,#RCC_CFGR] ldr r5,=#RCC_CFGR_SW_PLL orr r4,r5 str r4,[r7,#RCC_CFGR] Wait_PLL: ldr r4,[r7,#RCC_CFGR] ldr r5,=#RCC_CFGR_SWS and r4,r5 ldr r5,=#RCC_CFGR_SWS_PLL cmp r4,r5 bne Wait_PLL pop {r4,r5,r6,r7,lr} bx lr fail_startup: b fail_startup .end #file: gpio_d.s .include "macros.inc" .include "src/gpio_regs.inc" SET_TARGET
- 10. .text FUNCTION gpio_d_init, global // initialize all 16 bits of Port D to outputs push {lr} mov r0,#3 // send 1 as argument to rcc_gpio_enable function bl rcc_gpio_enable // call rcc_gpio_enable ldr r3,=#GPIOD_BASE // load r3 with base address of GPIO PORT D ldr r2,=#0x00000000 // load 0 into r2 str r2,[r3, #GPIO_PUPDR] // write 0 to GPIO Port D PUPD register str r2,[r3, #GPIO_OTYPER] // write 0 to GPIO Port D TYPE register str r2,[r3, #GPIO_ODR] // write 0 to GPIO Port D output data register ldr r2,=#0x55555555 // set all 16 bits of Port D to outputs str r2,[r3, #GPIO_MODER] ldr r2,=#0xffffffff // write 0xffffffff to Port D SPEED register str r2,[r3, #GPIO_OSPEEDR] pop {lr} bx lr ENDFUNC gpio_d_init
- 11. FUNCTION gpio_d_put, global push {lr} ldr r3,=#GPIOD_BASE str r0,[r3, #GPIO_ODR] pop {lr} bx lr ENDFUNC gpio_d_put FUNCTION gpio_d_get_current, global // get the current state of the 16 Port D outputs push {lr} ldr r3,=#GPIOD_BASE // load r3 with base address of GPIO Port D ldr r0,[r3, #GPIO_ODR] // load r0 (rtn arg) with GPIO Port D output data register pop {lr} bx lr ENDFUNC gpio_d_get_current .end #file: LEDR.s
- 12. .include "macros.inc" SET_TARGET .text FUNCTION LEDR_Init, global push {lr} bl gpio_d_init pop {lr} bx lr ENDFUNC LEDR_Init FUNCTION LEDR_Put_A, global push {lr} mov r1, r0 bl gpio_d_get_current ldr r2,=#(~(~0<<3)) and r1, r2 lsl r1,#8 lsl r2,#8 mvn r2,r2 and r0,r2 orr r0,r1 bl gpio_d_put pop {lr} bx lr
- 13. ENDFUNC LEDR_Put_A FUNCTION LEDR_Put_B, global push {lr} mov r1, r0 bl gpio_d_get_current ldr r2,=#(~(~0<<4)) and r1, r2 lsl r1, #2 lsl r2, #2 mvn r2, r2 and r0, r2 orr r0, r1 bl gpio_d_put pop {lr} bx lr ENDFUNC LEDR_Put_B .end //# Defines #define reload_value 0xFFFFFF /* System Timer reload value */ #define LEDs_ODR_Base 0x40020C14 /* LEDs Port D ODR Address */ //Function Declarations void SetSysClock(); void gpio_d_init(); unsigned int SysTick_Config(int reload);
- 14. unsigned int *pLEDs = (unsigned int*)LEDs_ODR_Base; /* Create pointer to Port D - ODR Reg */ int main() { SetSysClock(); //set system clock gpio_d_init(); //initialize Port D (LEDs) SysTick_Config(reload_value); //configure SysTick System Timer while(1) //loop forever { } return 0; } void SysTick_Handler (void) //ISR - SysTick Interrupt Service Routine { *pLEDs = *pLEDs ^ (1<<14); //toggle Port D - LED 15 }