Jason E Stephens’ Professional Accomplishments 2020

1. Jason E. Stephens Essex, VT * (845) 554-8430
jes_uo@me.com
www.linkedin.com/in/jestephens
Jason's Google Scholar Page
Semiconductor Pathfinding Master Inventor
Professional Accomplishments
Published academic author and inventor/co-inventor of 50 granted US patents and 30 patent applications in
process.
Published Works
Segment Removal Strategy in SAQP Technology for Advanced BEoL Application
International Interconnect Technology Conference (IITC) - 2017
Planarity Considerations in SADP for Advanced BEoL Patterning
International Interconnect Technology Conference (IITC) - 2017
Quantitative Projections of the Cost Benefit of 3D Integration
International Symposium on Microelectronics - October 2015
Challenges of Analog and I/O Scaling in 10nm SoC Technology and Beyond
Electron Devices Meeting (IEDM) - 2014
IEEE International, pp. 18.3.1 - 18.3.4
10nm Local Interconnect Challenge with Iso-dense Loading and Improvement with ALD Spacer
Process
IEEE International Interconnect Technology Conference/Advanced Metalization Conference- 2017
Phase Transitions in K2Cr207 and Structural Redeterminations of Phase II
Acta Crystallographic - December 2004
AWARDS, RECOGNITIONS & MEMBERSHIPS
๏ Master Inventor Achievement
๏ PM Project JumpStart Certification
๏ Excellence Award: GlobalFoundries Core Values and Behaviors: SLM Pad/Frame methodology. (Q4 2014)
๏ Excellence Award: GlobalFoundries Core Values and Behaviors – JDA TDR and Validation. (Q1 2014)
๏ GlobalFoundries Global Recognition Award for commitment and hard work on technology deliverables.
(4/2013)
๏ Excellence Award: GlobalFoundries Core Values and Behaviors – BEOL Achievements. (3/2012)
๏ Engineering Excellence Award: Developing & Supporting EBRs, saving ~203 wafers from scrap. (06/2007)
๏ Engineering Excellence Award: Quickly Developing and Implementing a Final Outgoing Insp. Method,
Procedure, Documentation, and Corrective Action Policy. (02/2007)
๏ BEoL Technical Patent Advocate Co-Chair for the Patent Review Board at GlobalFoundries.

2. Patents
๏ 9786545 - Method of forming ANA regions in an integrated circuit (http://www.pat2pdf.org/pat2pdf/
foo.pl?number=9786545)
๏ 10056373 - Transistor contacts self-aligned in two dimensions (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=10056373)
๏ 10181420 - Devices with chamfer-less vias multi-patterning & methods for forming chamfer-less vias
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=10181420)
๏ 10236350 - Method, apparatus and system for a high density middle of line flow.
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=10236350)
๏ 10262941 - Devices and methods for forming cross coupled contacts (http://www.pat2pdf.org/pat2pdf/
foo.pl?number=10262941)
๏ 10340180 - Merge mandrel features (http://www.pat2pdf.org/pat2pdf/foo.pl?number=10340180)
๏ 10522403 - Middle of the line self-aligned direct pattern contacts (http://www.pat2pdf.org/pat2pdf/
foo.pl?number=10522403)
๏ 10559503 - Methods, apparatus and system for a passthrough-based architecture
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=10559503)
๏ 8793627 - Via non-standard limiting parameters (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=8793627)
๏ 8839168 - Self-aligned double patterning via enclosure design (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=8839168)
๏ 8856715 - Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP)
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=8856715)
๏ 8946914 - Contact power rail (http://www.pat2pdf.org/pat2pdf/foo.pl?number=8946914)
๏ 8969199 - Methods of forming a circuit that includes a cross-coupling gate contact structure wherein
the circuit is to be manufactured using a triple patterning process (http://www.pat2pdf.org/pat2pdf/
foo.pl?number=8969199)
๏ 8987816 - Contact power rail (http://www.pat2pdf.org/pat2pdf/foo.pl?number=8987816)
๏ 9006100 - Middle-of-the-line constructs using diffusion contact structures (http://www.pat2pdf.org/
pat2pdf/foo.pl?number=9006100)
๏ 9142513 - Middle-of-the-line constructs using diffusion contact structures (http://www.pat2pdf.org/
pat2pdf/foo.pl?number=9142513)
๏ 9202751 - Transistor contacts self-aligned in two dimensions (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9202751)
๏ 9224617 - Forming cross-coupled line segments (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9224617)
๏ 9236437 - Method for creating self-aligned transistor contacts (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9236437)
๏ 9287186 - Method and structure for determining thermal cycle reliability (http://www.pat2pdf.org/
pat2pdf/foo.pl?number=9287186)
๏ 9412655 - Forming merged lines in a metallization layer by replacing sacrificial lines with conductive
lines (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9412655)
๏ 9436081 - Methods of modifying masking reticles to remove forbidden pitch regions thereof (http://
www.pat2pdf.org/pat2pdf/foo.pl?number=9436081)
๏ 9461128 - Method for creating self-aligned transistor contacts (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9461128)
๏ 9465907 - Multi-polygon constraint decomposition techniques for use in double patterning applications
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=9465907)
๏ 9472455 - Methods of cross-coupling line segments on a wafer (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9472455)

3. ๏ 9502528 - Borderless contact formation through metal-recess dual cap integration
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=9502528)
๏ 9576735 - Vertical capacitors with spaced conductive lines (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9576735)
๏ 9660040 - Transistor contacts self-aligned two dimensions (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9660040)
๏ 9691626 - Method of forming a pattern for interconnection lines in an integrated circuit wherein the
pattern includes gamma and beta block mask portions (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9691626)
๏ 9779943 - Compensating for lithographic limitations in fabricating semiconductor interconnect
structures (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9779943)
๏ 9812396 - Interconnect structure for semiconductor devices with multiple power rails and redundancy
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=9812396)
๏ 9818623 - Method of forming a pattern for interconnection lines and associated continuity blocks in an
integrated circuit (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9818623)
๏ 9818640 - Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal
lines (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9818640)
๏ 9818641 - Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an
array of metal lines (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9818641)
๏ 9818651 - Methods, apparatus and system for a passthrough-based architecture
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=9818651)
๏ 9825031 - Methods of forming a high-k contact liner to improve effective via separation distance and
the resulting devices (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9825031)
๏ 9852986 - Method of patterning pillars to form variable continuity cuts in interconnection lines of an
integrated circuit (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9852986)
๏ 10056373 - Transistor contacts self-aligned in two dimensions (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=10056373)
๏ 10181420 - Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=10181420)
๏ 10262941 - Devices and methods for forming cross coupled contacts (http://www.pat2pdf.org/pat2pdf/
foo.pl?number=10262941)
๏ 10340180 - Merge mandrel features (http://www.pat2pdf.org/pat2pdf/foo.pl?number=10340180)
๏ 8969199 - Methods of forming a circuit that includes a cross-coupling gate contact structure wherein
the circuit is to be manufactured using a triple patterning process (http://www.pat2pdf.org/pat2pdf/
foo.pl?number=8969199)
๏ 9660040 - Transistor contacts self-aligned two dimensions (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9660040)
๏ 9691626 - Method of forming a pattern for interconnection lines in an integrated circuit wherein the
pattern includes gamma and beta block mask portions (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=9691626)
๏ 9812396 - Interconnect structure for semiconductor devices with multiple power rails and redundancy
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=9812396)
๏ 9818623 - Method of forming a pattern for interconnection lines and associated continuity blocks in an
integrated circuit (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9818623)
๏ 9818640 - Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal
lines (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9818640)
๏ 9818641 - Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an
array of metal lines (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9818641)
๏ 9818651 - Methods, apparatus and system for a passthrough-based architecture
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=9818651)
๏ 9825031 - Methods of forming a high-k contact liner to improve effective via separation distance and
the resulting devices (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9825031)

4. ๏ 9852986 - Method of patterning pillars to form variable continuity cuts in interconnection lines of an
integrated circuit (http://www.pat2pdf.org/pat2pdf/foo.pl?number=9852986)
๏ 8598633 - Semiconductor device having contact layer providing electrical connections
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=8598633)
๏ 9530689 - Methods for fabricating integrated circuits using multi-patterning processes
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=9530689)
๏ 20170263715 - METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE
FLOW (http://www.pat2pdf.org/pat2pdf/foo.pl?number=20170263715)
๏ 20170250080 - COMPENSATING FOR LITHOGRAPHIC LIMITATIONS IN FABRICATING
SEMICONDUCTOR INTERCONNECT STRUCTURES
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=20170250080)
๏ 20170263506 - METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED
ARCHITECTURE (http://www.pat2pdf.org/pat2pdf/foo.pl?number=20170263506)
๏ 20170278720 - METHOD OF FORMING A PATTERN FOR INTERCONNECTION LINES AND
ASSOCIATED CONTINUITY BLOCKS IN AN INTEGRATED CIRCUIT
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=20170278720)
๏ 20180033701 - METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED
ARCHITECTURE (http://www.pat2pdf.org/pat2pdf/foo.pl?number=20180033701)
๏ 20180226294 - DEVICES WITH CHAMFER-LESS VIAS MULTI-PATTERNING AND METHODS FOR
FORMING CHAMFER-LESS VIAS
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=20180226294)
๏ 20190139823 - METHODS OF FORMING CONDUCTIVE LINES AND VIAS AND THE RESULTING
STRUCTURES (http://www.pat2pdf.org/pat2pdf/foo.pl?number=20190139823)
๏ 20190214298 - MIDDLE OF THE LINE SELF-ALIGNED DIRECT PATTERN CONTACTS
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=20190214298)
๏ 20190221474 - MERGE MANDREL FEATURES (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=20190221474)
๏ 20190267281 - MERGE MANDREL FEATURES (http://www.pat2pdf.org/pat2pdf/foo.pl?
number=20190267281)
๏ 20200083102 - MIDDLE OF THE LINE SELF-ALIGNED DIRECT PATTERN CONTACTS
(http://www.pat2pdf.org/pat2pdf/foo.pl?number=20200083102)