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Can IC testing Go Wireless?
Introduction to the HOY tester



        Soumalya Ghosh
                   (1304792)
           University of Alberta
   Electrical and Computer Engineering


           soumalya@ualberta.ca
             ECE 512 Fall 2012 Presentation
Outline
• Motivation
• IC testing strategies vs. VLSI technology
• Wireless testing – the new standard
  – Introduction to wireless testing
• Types of wireless testing techniques
  – RF Communication technique
  – NF Communication technique
  – Optical Communication technique
                                              contd. …


                                                     2
Outline (2)
• The new platform – HOY
    – Introduction to the HOY tester
•   The HOY approach
•   HOY operation
•   Advantages of HOY
•   Test flow (HOY)
•   Future work

                                       3
Motivation
• Probe card costs
• Probe card alignment issues
• Contact causes wear and tear in the chip
• Maintenance and cleaning issues of cards
• Testing is the only category of cost which
  doesn’t decrease with advanced fabrication1
• Increased pin count, speed, timing accuracy
  requirements
    1. Semiconductor Industry Association, ITRS Report, 2003 Edition, 2003
IC testing strategies vs. VLSI technology




                                       Fig. 1: Microprocessor clock rates2
2. Bushnell, Michael, and Vishwani Agrawal. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits.
Vol. 17. Springer, 2000.
The scenario




                             Table 1: VLSI Chips – present and future3




3. D. Herrell, "Power to the Package," IEEE Spectrum, vol. 36, no. 7, pp. 46-53, July 1999
Wireless testing – the new standard
• Replaces conventional i/o pins in probe cards
  with wireless links
• Specially suitable when pin density is very
  high in the DUT
• Higher reliability due to reduced mechanical
  stress
• No creation of debris
• Faster data rates possible than with cards
                                                  7
RF Communication technique
• Also called as ‘Far Field’ communication
  technique
• Transceivers are placed on the wafer
• Size overhead may result
• Provides long range
• Power supply considerations



                                             8
NF Communication technique
• Energy transmitted through varying EM field
  (quasi-static EM field)
• Consumes low power
• Eliminates reflection issues
• More efficient than RF technology for shorter
  distances



 Fig. 2: Near and far fields around
             RF source                            9
Optical Communication Technique
• High frequency EM fields
• Almost immune to interference
• Exploited using LDT (Laser Direct Testing)
  – Laser – metal interaction
  – Photoelectron emission, etc




                                               10
The new platform – HOY
Developers are:
  Cheng Wen Wu, Shi-Yu Huang, Po-Chiun Huang,
  Tsin-Yuan Chang and Yu-Tsao Hsing,
  Dept. of Computer Science, National Tsing Hua
  University, Taiwan
and
  Chih-Tsun Huang
  Dept. of Electrical Engineering, National Tsing
  Hua University, Taiwan
                                                                                                           contd. …

 Wu, Cheng-Wen, et al. "The HOY tester-Can IC testing go wireless?." VLSI Design, Automation and Test, 2006 International
 Symposium on. IEEE, 2006.
Introduction to the HOY tester
• A novel wireless test system with enhanced
  embedded test features
• Conceived in 2003, launched in 2005, called
  HOY – (Hypothesis, Odyssey and Yield)
• Provides test solutions for wafer test, final test
  after packaging and field tests and diagnostics
• Reduced capital investment, simplified test
  flow and increased parallelism reduces cost

                                                   12
The HOY approach

                   Odyssey


Hypothesis                              Yield



                  HOY
             Fig. 3: The HOY approach

                                                13
Hypothesis
It is getting harder for the ATE :
  i.   to keep up with the pin count, speed and timing
       accuracy
  ii. to maintain reasonable cost level and satisfy
       above requirements
  iii. to maintain quality and yield for wafers bare dies
       and packaged chips
 According to the HYPOTHESIS, we can solve
  all these issues with wireless test
                                                        14
Odyssey
• HOY is a long term project with some key
  technologies still immature
• We expect the technological expertise
  required for the implementation of HOY be
  available sometime in the recent future
• Within 10 years time significant portion of IC
  testing to go wireless


                                                   15
Odyssey (2)

          Fig. 4: HOY applications:

          a) Wafer test

          b) Chip test

          c) Field diagnosis




                                      16
Yield
1. It performs wafer-level test and burn-in
2. It supports at-speed testing (by BIST)
3. It greatly improves the defect level before the
   dies are packaged
However,
1. Complete BIST (and BISR) solutions
2. Stable and low cost wireless communication
3. Contactless power supply, security, pin/pad test

                                                      17
HOY operation




Fig. 5: The HOY test system with contactless power supply

                                                            18
Advantages of HOY
• It performs wafer level test and burn-in
• It supports at-speed testing (by BIST)
• It greatly improves the defect level before the
  dies are packaged
• In conventional test flow there are redundant
  tests
• Wafer level burn-in and test can be done in a
  more cost-effective way
• Bottleneck in pin count is removed

                                                    19
Test flow (HOY)
Greatly simplified test runs:
• Burn-in is done at the wafer level
• Both burn-in and wafer level tests are by BIST
• Further tests depend on packaging needs
     – If packaged, final tests are done after packaging
     – If not, KGD (known-good-die) should be
       guaranteed up to the allowable defect level
• Final test contains pin test, basic functional
  test, AC test and speed sort
Wu, Cheng-Wen, et al. "The HOY tester-Can IC testing go wireless?." VLSI Design, Automation and Test, 2006 International
Symposium on. IEEE, 2006.
Test flow (HOY) (2)
• For non-packaged dies all tests are completed
  at the wafer level
• BISR repairs after the BIST detects any fault
• CUTs have their own BISR module in-built




Wu, Cheng-Wen, et al. "The HOY tester-Can IC testing go wireless?." VLSI Design, Automation and Test, 2006 International
Symposium on. IEEE, 2006.
Future work
Proposed technologies for HOY:
  A. Enhanced Embedded Test Features
  B. Wireless Transmission and Contactless Power
  C. Test Interface and Testers
  D. Protocols, ID and Security




                                                   23
References
1. Semiconductor Industry Association, ITRS Report,
   2003 Edition, 2003
2. Bushnell, Michael, and Vishwani Agrawal. Essentials
   of electronic testing for digital, memory, and mixed-
   signal VLSI circuits. Vol. 17. Springer, 2000.
3. D. Herrell, "Power to the Package," IEEE Spectrum,
   vol. 36, no. 7, pp. 46-53, July 1999
4. Wu, Cheng-Wen, et al. "The HOY tester-Can IC testing
   go wireless?." VLSI Design, Automation and Test, 2006
   International Symposium on. IEEE, 2006.


                                                       24
Questions




            25

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Soumalya-HOY tester-University of Alberta (ECE 512)

  • 1. Can IC testing Go Wireless? Introduction to the HOY tester Soumalya Ghosh (1304792) University of Alberta Electrical and Computer Engineering soumalya@ualberta.ca ECE 512 Fall 2012 Presentation
  • 2. Outline • Motivation • IC testing strategies vs. VLSI technology • Wireless testing – the new standard – Introduction to wireless testing • Types of wireless testing techniques – RF Communication technique – NF Communication technique – Optical Communication technique contd. … 2
  • 3. Outline (2) • The new platform – HOY – Introduction to the HOY tester • The HOY approach • HOY operation • Advantages of HOY • Test flow (HOY) • Future work 3
  • 4. Motivation • Probe card costs • Probe card alignment issues • Contact causes wear and tear in the chip • Maintenance and cleaning issues of cards • Testing is the only category of cost which doesn’t decrease with advanced fabrication1 • Increased pin count, speed, timing accuracy requirements 1. Semiconductor Industry Association, ITRS Report, 2003 Edition, 2003
  • 5. IC testing strategies vs. VLSI technology Fig. 1: Microprocessor clock rates2 2. Bushnell, Michael, and Vishwani Agrawal. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Vol. 17. Springer, 2000.
  • 6. The scenario Table 1: VLSI Chips – present and future3 3. D. Herrell, "Power to the Package," IEEE Spectrum, vol. 36, no. 7, pp. 46-53, July 1999
  • 7. Wireless testing – the new standard • Replaces conventional i/o pins in probe cards with wireless links • Specially suitable when pin density is very high in the DUT • Higher reliability due to reduced mechanical stress • No creation of debris • Faster data rates possible than with cards 7
  • 8. RF Communication technique • Also called as ‘Far Field’ communication technique • Transceivers are placed on the wafer • Size overhead may result • Provides long range • Power supply considerations 8
  • 9. NF Communication technique • Energy transmitted through varying EM field (quasi-static EM field) • Consumes low power • Eliminates reflection issues • More efficient than RF technology for shorter distances Fig. 2: Near and far fields around RF source 9
  • 10. Optical Communication Technique • High frequency EM fields • Almost immune to interference • Exploited using LDT (Laser Direct Testing) – Laser – metal interaction – Photoelectron emission, etc 10
  • 11. The new platform – HOY Developers are: Cheng Wen Wu, Shi-Yu Huang, Po-Chiun Huang, Tsin-Yuan Chang and Yu-Tsao Hsing, Dept. of Computer Science, National Tsing Hua University, Taiwan and Chih-Tsun Huang Dept. of Electrical Engineering, National Tsing Hua University, Taiwan contd. … Wu, Cheng-Wen, et al. "The HOY tester-Can IC testing go wireless?." VLSI Design, Automation and Test, 2006 International Symposium on. IEEE, 2006.
  • 12. Introduction to the HOY tester • A novel wireless test system with enhanced embedded test features • Conceived in 2003, launched in 2005, called HOY – (Hypothesis, Odyssey and Yield) • Provides test solutions for wafer test, final test after packaging and field tests and diagnostics • Reduced capital investment, simplified test flow and increased parallelism reduces cost 12
  • 13. The HOY approach Odyssey Hypothesis Yield HOY Fig. 3: The HOY approach 13
  • 14. Hypothesis It is getting harder for the ATE : i. to keep up with the pin count, speed and timing accuracy ii. to maintain reasonable cost level and satisfy above requirements iii. to maintain quality and yield for wafers bare dies and packaged chips  According to the HYPOTHESIS, we can solve all these issues with wireless test 14
  • 15. Odyssey • HOY is a long term project with some key technologies still immature • We expect the technological expertise required for the implementation of HOY be available sometime in the recent future • Within 10 years time significant portion of IC testing to go wireless 15
  • 16. Odyssey (2) Fig. 4: HOY applications: a) Wafer test b) Chip test c) Field diagnosis 16
  • 17. Yield 1. It performs wafer-level test and burn-in 2. It supports at-speed testing (by BIST) 3. It greatly improves the defect level before the dies are packaged However, 1. Complete BIST (and BISR) solutions 2. Stable and low cost wireless communication 3. Contactless power supply, security, pin/pad test 17
  • 18. HOY operation Fig. 5: The HOY test system with contactless power supply 18
  • 19. Advantages of HOY • It performs wafer level test and burn-in • It supports at-speed testing (by BIST) • It greatly improves the defect level before the dies are packaged • In conventional test flow there are redundant tests • Wafer level burn-in and test can be done in a more cost-effective way • Bottleneck in pin count is removed 19
  • 20. Test flow (HOY) Greatly simplified test runs: • Burn-in is done at the wafer level • Both burn-in and wafer level tests are by BIST • Further tests depend on packaging needs – If packaged, final tests are done after packaging – If not, KGD (known-good-die) should be guaranteed up to the allowable defect level • Final test contains pin test, basic functional test, AC test and speed sort Wu, Cheng-Wen, et al. "The HOY tester-Can IC testing go wireless?." VLSI Design, Automation and Test, 2006 International Symposium on. IEEE, 2006.
  • 21. Test flow (HOY) (2) • For non-packaged dies all tests are completed at the wafer level • BISR repairs after the BIST detects any fault • CUTs have their own BISR module in-built Wu, Cheng-Wen, et al. "The HOY tester-Can IC testing go wireless?." VLSI Design, Automation and Test, 2006 International Symposium on. IEEE, 2006.
  • 22. Future work Proposed technologies for HOY: A. Enhanced Embedded Test Features B. Wireless Transmission and Contactless Power C. Test Interface and Testers D. Protocols, ID and Security 23
  • 23. References 1. Semiconductor Industry Association, ITRS Report, 2003 Edition, 2003 2. Bushnell, Michael, and Vishwani Agrawal. Essentials of electronic testing for digital, memory, and mixed- signal VLSI circuits. Vol. 17. Springer, 2000. 3. D. Herrell, "Power to the Package," IEEE Spectrum, vol. 36, no. 7, pp. 46-53, July 1999 4. Wu, Cheng-Wen, et al. "The HOY tester-Can IC testing go wireless?." VLSI Design, Automation and Test, 2006 International Symposium on. IEEE, 2006. 24
  • 24. Questions 25

Editor's Notes

  1. Stuck at faults are most effective when applied at the circuit’s rated clock speed [501], rather than at a lower speed. Stuck at faults cover all (or most) circuit signals assuming that a signal may be permanently stuck-at logic 0 or 1.