The document describes a system-on-a-chip (SoC) for non-destructive testing (NDT). The SoC contains an FPGA with a MicroBlaze microprocessor as the control unit. It has interfaces for Ethernet, USB, LVDS I/O, SDRAM memory, and flash memory for bootloading and configuration. Power is supplied via a single 4-8V input with internal DC-DC converters. The entire system is implemented on a credit card-sized board.

1. SoC for NDT JOSE MIGUEL MORENO LLAMAS CAEND - CSIC

2. JOSE MIGUEL MORENO LLAMAS 2 SoC for NDT Block Diagram

4. MicroBlaze Microprocessor.

5. Memory Controller

6. Ethernet MAC Controller

7. I/O LVDS INTERFACE Capability

8. USB 2.0 Controller

9. Gigabit Ethernet PHY Controller.

10. SDRAM DDR3 Memory(128MByte – 1Gbit)

11. Boot loader Flash Memory (16MByte – 128Mbit)

12. Configuration SPI Flash Memory (8MByte – 64Mbit)

13. Onepowersupply input (4-8V 5A), withinternal DC-DC converters for supplies all circuitry.

14. JTAG and USB to SPI flash-FPGA configuration capability.JOSE MIGUEL MORENO LLAMAS 3 DESCRIPTION