report-1.pdf

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Bangladesh University
A Center of Excellence for Higher Education
A report on,
Designing a simple 8-bit Arithmetic Logic Unit (ALU) which will
perform Arithmetic, Bitwise and Logical operation.
Submitted to the Department of Computer Science and Engineering,
Bangladesh University, in partial fulfillment of the requirements for the
degree of,
Bachelor of Engineering
in
Computer Science And Engineering
by
Md. Saiduzzaman
ID: 202011056021
Under the guidance of,
Md. Tariqul Islam
Lecturer & Coordinator (Evening)
Department of CSE, Bangladesh University

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(A Center of Excellence for Higher Education)
Department of Computer Science and Engineering
5/B, Beribandh Main Road, Adabar, Mohammadpur, Dhaka-1207
CERTIFICATE
Certified that the project work entitled “Designing a simple 8-bit Arithmetic Logic Unit
(ALU) which will perform Arithmetic, Bitwise and Logical operation. Carried out by
Md. Saiduzzaman, ID-202011056021 is an sincere student of Bangladesh University for
passing the „Project & Thesis I‟ during the semester spring-2023. The project report has
been approved as it satisfies the academic requirement in respect of project work
prescribed for the said degree.
Md. Tariqul Islam
Lecturer & Coordinator CSE (evening)

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(A Center of Excellence for Higher Education)
Department of Computer Science and Engineering
5/B, Beribandh Main Road, Adabar, Mohammadpur, Dhaka-1207
DECLARATION
Myself, Md. Saiduzzaman students of Tenth Semester B.E., in the Department of
Computer Science and Engineering, Bangladesh University, Dhaka-1207 declare that the
project entitled “Designing a simple 8-bit Arithmetic Logic Unit (ALU) which will
perform Arithmetic, Bitwise and Logical operation” has been carried out by me and
submitted in partial fulfillment of the course requirements for the award of degree in
Bachelor of Engineering in Computer Science and Engineering of Bangladesh
University, Dhaka-1207 during the semester Spring-2023. The matter embodied in this
report has not been submitted to any other university or institution for the award of any
other degree or diploma.
Department of Computer Science And Engineering
Dhaka-1207
Md. Saiduzzaman
ID: 202011056021

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ACKNOWLEDGMENT
A number of personalities, in their own capacities have helped me in carrying out this
project work. I would like to take this opportunity to thank them all.
First and foremost I would like to thank Md. Sadiq Iqbal Sir head of the Department for
his overall support towards completing my project work.
I would like to thank our honorable department coordinator Mst. Rokeya Khatun mam,
for helping me with providing updated information and guidelines for project preparation.
I deeply express my sincere gratitude to my project mentor Md. Tariqul Islam sir, for his
guidance, regular source of encouragement and assistance throughout this project.
I thank my Parents, and all the Faculty members of Department of Computer Science &
Engineering for their constant support and encouragement.
Last, but not the least, I am thanking my honorable lecturer Md Zakir Hossain sir for his
excellent teaching about VLSI which encourage myself to choose that project field.

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ABSTRACT
This project aims to design a simple 8-bit Arithmetic Logic Unit (ALU) capable of
performing a range of operations including arithmetic, bitwise, and logical operations.
The ALU serves as a fundamental building block in computer processors, enabling
mathematical computations and logical evaluations. The project involves the design and
implementation of the ALU using basic logic gates and digital circuits.
The design process will involve breaking down the ALU into individual components,
such as adders, multiplexers, and logic gates, and implementing them using digital logic.
The project will employ a combinational logic approach, focusing on the instantaneous
outputs based on the current inputs without the need for internal memory.
The ALU's functionality and correctness will be verified through simulation and testing.
The project will utilize hardware description languages (HDL) and simulation tools to
model and validate the ALU's behavior. Performance evaluation will consider factors
such as speed, area utilization, and power consumption.
The successful completion of this project will yield an operational 8-bit ALU capable of
executing arithmetic, bitwise, and logical operations. The designed ALU will serve as a
foundation for further exploration and integration into larger digital systems. The
project's outcomes contribute to the understanding and implementation of basic digital
logic and provide valuable insights into ALU design principles and considerations.

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Table of Contents
Chapter 1
Introduction
1.1 Introduction……………………………………………………………………………………………1
1.2 Objectives……………………………………………………………………………………………..1
1.3 Scope…………………………………………………………………………………………………..2
1.3.1 ALU Architecture ………………………………………………………………………………..2
1.3.2 Arithmetic Operations……………………………………………………………………………2
1.3.3 Bitwise Operations ………………………………………………………………………………2
1.3.4 Logical Operations……………………………………………………………………………….2
1.3.5 Digital Logic Implementation …………………………………………………………………..3
1.3.6 Simulation and Testing…………………………………………………………………………..3
1.3.7 Performance Evaluation ………………………………………………………………………...3
1.3.8 Documentation and Reporting ………………………………………………………………….3
1.4 Issues…………………………………………………………………………………………………..3
1.4.1 Incorrect Output………………………………………………………………………………….3
1.4.2 Timing Violations………………………………………………………………………………..3
1.4.3 Performance Bottlenecks………………………………………………………………………...4
1.4.4 Glitches and Metastability……………………………………………………………………….4
1.4.5 Resource Constraints…………………………………………………………………………….4
1.4.6 Negative, Zero and Overflow Output……………………………………………………………4
1.5 Solution Analysis …………………………………………………..………………………………...5
Chapter 2
Requirement Specifications
2.1 Functional Requirements……………………………………………………………………………...6
2.1.1 Arithmetic Operations……………………………………………………………………………6
2.1.2 Bitwise Operations………………………………………………………………………………6
2.1.3 Logical Operations ………………………………………………………………………………6
2.1.4 Input and Output…………………………………………………………………………………6
2.2 Non-functional Requirements…………………………………………………………………………6
2.2.1 Power Consumption……………………………………………………………………………..7
2.2.2 Performance……………………………………………………………………………………...7
2.2.3 Accuracy…………………………………………………………………………………………7
2.2.4 Resource Utilization and simplicity……………………………………………………………..7
2.3 User Requirements…………………………………………………………………………………….7
2.4 System Requirements………………………………………………………………………………….8
2.4.1 Hardware Requirements……………………………………………….....................................8
2.4.2 Software Requirements…………………………………………………………………………..8
2.4.3 System Performance……………………………………………………………………………..8

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Chapter 3
Used Tools Gates And Circuits
3.1 Used Tools…………………………………………………………………………………………....9
3.1.1 Verilog HDL…………………………………………………………………………………….9
3.1.2 Xilinx Vivado Design Suit………………………………………………………………………9
3.1.3 VS Code With Verilog HDL Extension…………………………………………………………9
3.1.4 Logisim…………………………………………………………………………………………..9
3.2 Basic Gates And Circuits…………………………………………………………………………….10
3.2.1 AND Gate………………………………………………………………………………………10
3.2.2 Or Gate………………………………………………………………………………………….10
3.2.3 Not Gate………………………………………………………………………………………...11
3.2.4 X-OR/X-NOR Gate…………………………………………………………………………….11
3.2.5 Adder……………………………………………………………………………………………11
3.2.6 Multiplexor……………………………………………………………………………………..12
Chapter 4
Adopted Methodology
4.1 RTL-Designing………………………………………………………………………………………13
4.2 Combinational Logic Design………………………………………………………………………..14
4.3 Logic Synthesis………………………………………………………………………………………14
4.3.1 High-Level Behavioral Description…………………………………………………………….14
4.3.2 Technology Mapping…………………………………………………………………………...15
4.3.3 Netlist Generation………………………………………………………………………………15
4.3.4 Optimization……………………………………………………………………………………15
4.3.5 Timing Analysis………………………………………………………………………………..15
4.3.6 Technology Constraints………………………………………………………………………...15
4.3.7 Verification……………………………………………………………………………………..15
4.3.8 Design-for-Testability (DFT)…………………………………………………………………...15
Chapter 5
Result Analysis
5.1 Definition …………………………………………………………………………………………....16
5.2 Basic Block Diagram………………………………………………………………………………...16
5.3 Truth Table of 8-Bit ALU……………………………………………………………………………17
5.4 Timing Signal /Wave………………………………………………………………………………...18
5.4.1 Close Observation of Arithmetic Operation……………………………………………………18
5.4.2 Close Observation of Bitwise Operation……………………………………………………....19
5.4.3 Close Observation of Logical Operation……………………………………………………….19
5.5 RTL Schematic Diagram…………………………………………………………………………….20

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Chapter 6
Market Research And Adaptability
6.1 Legacy Systems………………………………………………………………………………...……21
6.2 Embedded Systems ………………………………………………………………………………….21
6.3 Low-Power Applications ……………………………………………………………………………21
6.4 Education and Learning……………………………………………………………………………...21
6.5 Technological Advancements ……………………………………………………………………….21
Chapter 7
Conclusion, Future Work And References
7.1 Conclusion…………………………………………………………………………………………...22
7.2 Future Work……………………………………………………………………………………….....23
7.3 References……………………………………………………………………………………………23

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Chapter 1
INTRODUCTION
1.1 Introduction
 The recent progress in the field of computer science has lead to the reducing cost and growing
computing power of the hardware.
 In the rapidly evolving field of computer architecture and digital logic design, Arithmetic Logic
Units (ALUs) play a crucial role in enabling various computational operations within processors.
 An ALU is a fundamental component responsible for performing arithmetic operations, bitwise
operations, and logical operations on binary numbers.
 And the efficient steps to improve computational power of our device is to build an efficient
Arithmetic Logic Unit (ALU).
 ALU is an part of CPU and responsible for performing complex computational operations.
 Designing an 8-bit ALU requires careful consideration of the logic gates and circuits.
 Efficient design of the ALU also requires minimizing number of gates used and optimizing for
speed and power consumption.
 Overall, the design of an 8-bit ALU is a complex task that requires a deep understanding of
digital logic design.
1.2 Objectives
The primary objectives of this project include developing a functional ALU that can perform arithmetic
operations such as addition, subtraction, and multiplication on 8-bit binary numbers. Additionally, the
ALU will support bitwise operations like AND, OR, XOR, and complementation. Logical operations
such as equality checks and comparisons will also be incorporated.
 The main purpose of designing an 8-bit ALU is to create a reliable, efficient, and flexible
component of a CPU.

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 To handle unsigned and signed numbers and to detect errors such as carry and overflow flags
during arithmetic operations.
 Designing the ALU with pipelining and parallel processing capabilities.
 Here used Register Transfer Level designing which is a widely used methodology for designing
ALU‟s.
1.3 Scope
By addressing these scope elements, the project aims to deliver a functional 8-bit ALU that performs
arithmetic, bitwise, and logical operations accurately. The scope encompasses various aspects of ALU
design, digital logic implementation, simulation, testing, and performance evaluation, contributing to a
holistic understanding of ALU functionality and its application in computer systems. Here are the scope
elements that will be addressed:
1.3.1 ALU Architecture
The project involves defining the architecture of the 8-bit ALU, including the selection of appropriate
components such as adders, multiplexers, and logic gates. The architecture will determine the ALU's
capabilities, input/output configuration, and internal organization.
1.3.2 Arithmetic Operations
The ALU will be designed to perform common arithmetic operations on 8-bit binary numbers, such as
addition, subtraction, and multiplication. The project will focus on developing efficient and accurate
arithmetic circuits to execute these operations.
1.3.3 Bitwise Operations
The ALU will support bitwise operations, including logical AND, OR, XOR, and complementation. The
project will incorporate the necessary logic circuits and components to enable these bitwise operations
on 8-bit binary numbers.
1.3.4 Logical Operations
The ALU will be capable of executing logical operations such as equality checks, comparisons, and
logical shifts. The project will implement the required logic circuits to perform these logical operations
effectively.

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1.3.5 Digital Logic Implementation
The project will involve implementing the ALU's components and circuits using digital logic
techniques. This includes designing and connecting logic gates, multiplexers, adders, and other relevant
building blocks to create the ALU's desired functionality.
1.3.6 Simulation and Testing
The designed ALU will undergo rigorous simulation and testing to ensure its correctness and
performance. Hardware description languages (HDL) and simulation tools will be utilized to validate the
ALU's behavior, analyze its outputs, and verify its adherence to the desired specifications.
1.3.7 Performance Evaluation
The project will assess the performance characteristics of the ALU, considering factors such as speed,
area utilization, and power consumption. Comparative analysis may be performed to evaluate the
efficiency and effectiveness of the designed ALU.
1.3.8 Documentation and Reporting
The project scope includes the creation of comprehensive documentation and reports, detailing the
design methodology, circuit diagrams, simulation results, and performance analysis. Clear
documentation will facilitate understanding, reproducibility, and future enhancements of the ALU
design.
1.4 Issues
1.4.1 Incorrect Output
One of the critical issues that may arise is when the designed ALU produces incorrect outputs for certain
input combinations. Analysis of this issue may involve reviewing the circuitry, logic gates, and
interconnections to identify any potential errors in the design or implementation. Careful examination of
the timing diagrams and signal flow can help pinpoint where the issue might lie.
1.4.2 Timing Violations
Timing violations occur when signals do not meet the required setup and hold times, leading to
unexpected behavior or incorrect outputs. Analyzing timing violations involves examining signal paths,
delays, and ensuring proper synchronization between different components. Adjustments in gate delays,
pipeline stages, or critical paths might be necessary to resolve timing issues.

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1.4.3 Performance Bottlenecks
The ALU's performance might not meet the desired speed or efficiency targets due to bottlenecks in the
design. Analysis of performance bottlenecks involves identifying areas of the circuit where delays or
resource utilization is higher than expected. Optimizations such as parallelization, pipelining, or
component replacements can be explored to improve performance.
1.4.4 Glitches and Metastability
Glitches or metastability can cause momentary incorrect outputs or unstable behavior in the ALU.
Analysis of such issues requires examining the critical signal paths and ensuring proper synchronization
and stabilization. Techniques like adding flip-flops or synchronization elements can be employed to
mitigate these issues.
1.4.5 Resource Constraints
The design of the ALU might exceed the available resources, such as gate count, power, or area
limitations. Analyzing resource constraints involves assessing the design's size, complexity, and
resource utilization against the project requirements. Reducing gate count, optimizing circuitry, or
adopting alternative component choices might be necessary to fit within the given constraints.
1.4.6 Negative, Zero and Overflow Output
 The negative output indicates whether the result of an arithmetic operation is negative. In an 8-
bit ALU, the most significant bit (MSB) of the result is often used as the negative output. If the
MSB is 1, it signifies a negative value. Conversely, if the MSB is 0, the result is considered non-
negative.
 The zero output indicates whether the result of an arithmetic operation is equal to zero. It
provides information about whether the operands involved in the operation produced a result of
zero. When all bits of the result are zero, the zero output signal is asserted. If any bit of the result
is non-zero, the zero output is de-asserted.
 The overflow output indicates when an arithmetic operation produces a result that exceeds the
representable range of the ALU. In an 8-bit ALU, overflow occurs when the result of an
operation exceeds the range from -128 to 127 for signed numbers or from 0 to 255 for unsigned
numbers. The overflow output is typically triggered when the carry-out of the most significant
bit (MSB) and the carry-in of the MSB differ.

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1.5 Solution Analysis
Addressing these potential issues requires careful planning, attention to detail, and a systematic
approach to design, simulation, testing, and documentation. It's important to note that the specific issues
and their analysis will depend on the project's implementation, design choices, and the tools used.
Systematic problem-solving, thorough analysis, and an iterative approach to design and testing can help
overcome these issues and ensure the successful completion of the ALU project.

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Chapter 2
REQUIREMENT SPECIFICATIONS
2.1 Functional Requirements
These specify the specific functionalities, capabilities, and behavior expected from the system or
product. Functional requirements define what the system should do and the tasks it should be able to
perform.
2.1.1 Arithmetic Operations
The ALU should support arithmetic operations such as addition, subtraction, and multiplication on 8-bit
binary numbers. It should accurately perform these operations and provide correct results within a
specified range.
2.1.2 Bitwise Operations
The ALU should be capable of executing bitwise operations including logical AND, OR, XOR, and
complementation on 8-bit binary numbers. It should accurately perform these operations and provide
correct output based on the specified logic.
2.1.3 Logical Operations
The ALU should support logical operations such as equality checks, comparisons, and logical shifts on
8-bit binary numbers. It should accurately perform these operations and provide the expected results.
2.1.4 Input and Output
The ALU should have appropriate inputs and outputs for accepting input values, specifying the
operation to be performed, and providing the output result. The inputs and outputs should be compatible
with standard digital logic levels.
2.2 Non-functional Requirements
Non-functional requirements focus on the qualities and characteristics of the system or product rather
than its specific functionalities. These requirements include criteria related to performance, reliability,
security, usability, maintainability, and the overall system quality.

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2.2.1 Power Consumption
Main goal is to Consume low power to reduce the overall power consumption. The power consumption
of the project can vary depending on several factors, which includes:
 Component Selection.
 Clock Frequency.
 Activity and Switching.
 Voltage Levels.
 Power Management Techniques.
 Testing and Optimization.
2.2.2 Performance
The ALU should demonstrate efficient performance, with fast execution of operations and minimal
delays. It should provide results within an acceptable timeframe.
2.2.3 Accuracy
The ALU should produce accurate results for all supported operations. It should adhere to defined
mathematical rules and logic principles.
2.2.4 Resource Utilization and simplicity
The ALU should utilize hardware resources effectively, minimizing gate count and optimizing area
utilization. And the design should prioritize simplicity and ease of understanding to facilitate
comprehension, troubleshooting, and future modifications.
2.3 User Requirements
User requirements represent the needs, expectations, and goals of the end-users or stakeholders of the
system. These requirements focus on the user experience, usability, and user interface aspects to ensure
the system meets user needs effectively.
The ALU should have a user-friendly interface that allows users to input values, select the desired
operation, and retrieve the output result easily. Clear and comprehensive documentation should be
provided, including instructions on how to use the ALU, circuit diagrams, and explanations of its
functionality.

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2.4 System Requirements
System requirements cover technical aspects such as hardware, software, network, and infrastructure
requirements. These specifications define the necessary technical components, configurations, and
integrations required for the system to function correctly.
2.4.1 Hardware Requirements
The system should utilize digital logic components such as logic gates, multiplexers, adders, and
registers to implement the ALU. The system should incorporate a clock source to provide the necessary
timing for the ALU's operations. The clock source should have a frequency that satisfies the project's
performance requirements. The system should have a stable and appropriate power supply to ensure
reliable operation of the ALU and other components.
2.4.2 Software Requirements
Software tools such as hardware description languages (HDLs) and simulation software should be
available to facilitate the design, simulation, and verification of the ALU. Examples of HDLs include
VHDL or Verilog. The system should have access to a simulation environment that supports the chosen
HDL and allows for the testing and verification of the ALU design. Software tools for creating
documentation, circuit diagrams, and reports should be available to document the ALU design and
project details effectively.
2.4.3 System Performance
The ALU should be capable of performing arithmetic, bitwise, and logical operations within acceptable
timeframes, meeting the project's performance requirements. The ALU should produce accurate results
for all supported operations, adhering to mathematical rules and logic principles. The ALU's design
should optimize the utilization of hardware resources, such as gate count and area utilization, to ensure
efficient operation within the system.
Note: The ALU should be designed to occupy a minimum area and size.

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Chapter 3
USED TOOLS, GATES OR CIRCUITS
3.1 Used Tools
The selection of specific tools may depend on personal preference, project requirements, and the
designer's familiarity with the tools. It is important to choose tools that best suit the project's needs and
enable efficient design, simulation, and documentation processes. Here I have used,
3.1.1 Verilog HDL
Verilog is another popular hardware description language used for modeling and simulating digital
systems. It allows for the description of the structure and behavior of hardware components and can be
used to design and test the ALU.
3.1.2 Xilinx Vivado Design Suit
Here „Vivado ML edition‟ has been used, which is the version of „Xilinx Vivado Design Suit‟. It‟s
mainly used for Synthesis and Analysis of HDL‟s (Hardware Description Language). Vivado ML
edition provides a comprehensive development environment for designing, implementing, and deploying
machine learning algorithms on Xilinx FPGAs. It offers advanced tools and features that facilitate the
acceleration of machine learning workloads using FPGA technology.
3.1.3 VS Code With Verilog HDL Extension
Visual Studio Code (VS Code) is a popular, lightweight, and versatile source code editor developed by
Microsoft. I have used this editor for it‟s user friendly, flexible and simple user interface. It‟s also easy
to use for various types of language just adding their extensions. I have used it for mainly generating
timing diagram with the help of a testbench code.
3.1.4 Logisim
I have used Logisim as a simulation tool. Logisim is a free and open-source digital logic simulation tool
that allows users to design and simulate digital circuits. It provides a graphical user interface (GUI) for
designing and simulating circuits using a variety of logic gates, flip-flops, multiplexers, registers, and
other digital components.

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3.2 Basic Gates And Circuits
An 8-bit ALU typically consists of several logic gates and circuits that perform arithmetic Bitwise and
logical operations. Here are some basic gates and circuits that has been combined in various ways to
design the ALU.
3.2.1 AND Gate
Basically and gate has two input and one output terminal. But input can be more than two depending on
the required operations. When at least one input is zero (0) then output is zero (0). And when all input is
one (1) then only output is one (1). It‟s truth table and logic circuit basically looks like,
3.2.2 Or Gate
Similarly, OR gate also has two input and one output. But input can be more than two depending on the
operations. Here, output is zero (0) when all input is zero. And output is one(1) when at least one input
is one (1). We can understand clearly from this truth table and logic circuit given below.
Input A Input B Output Q
0 0 0
0 1 0
1 0 0
1 1 1
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 1
Input A
Input B
Output Q
Fig. 3.1 And gate
Table 3.1 Truth table of and gate
Input A
Input B
Output Q
Fig. 3.2 OR gate
Table 3.2 Truth table of or gate

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3.2.3 Not Gate
The NOT gate, also known as an inverter, is a fundamental logic gate that operates on a single input
signal and produces the logical negation (complement) of that input. Here's an representation of how a
NOT gate works:
3.2.4 X-OR/X-NOR Gate
The XOR gate, also known as the Exclusive OR gate, is a fundamental logic gate that operates on two
input signals and produces an output based on the exclusive disjunction (XOR operation) of the input
values. The behavior of an XOR gate can be described using a truth table.
Note: X-nor operation is exactly opposite or inversion of X-or.
3.2.5 Adder
A adder is a basic digital circuit used in binary arithmetic to add two single-bit binary numbers.
Basically it has two inputs, A and B, representing the two bits to be added, and two outputs, Sum (S) and
Carry (C). The behavior of an Half Adder describing below using a truth table.
Input Output
0 1
1 0
Input A Input B Output X
0 0 0
0 1 1
1 0 1
1 1 0
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table 3.3 Truth table of Not gate
Input Output
Fig. 3.3 Not gate
Table 3.4 Truth table of X-OR gate
Fig. 3.4 X-OR gate
Table 3.5 Truth table of Half Adder
Fig. 3.5 Half Adder

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3.2.6 Multiplexor
A multiplexer (mux) is a digital circuit that selects one of input signals from the given input and routes
it to the output based on the control signal. It is also known as a data selector or a data multiplexer. The
behavior of a mux can be described using a truth table that shows the possible combinations of input
data and the resulting output based on the control signal.
Selection Input A Input B Output
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Table 3.6 Truth table of 2*1 Mux
Fig. 3.6 2*1 Mux

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Chapter 4
ADOPTED METHODOLOGY
There are several methodologies that can be used to design an 8-bit Arithmetic Logic Unit (ALU). Here
I used Register Transfer Level designing (RTL-designing), Combinational Logic Design, Logic
Synthesis.
4.1 RTL-Designing
RTL (Register-Transfer Level) Designing is a methodology used in digital circuit design to describe and
implement complex digital systems at a higher level of abstraction. RTL focuses on the behavior and
data flow of a digital circuit using registers to capture and store information during the computation
process.
 Widely used methodology for designing digital circuits, including ALUs.
 RTL Designing is one step above the gate-level design and one step below the behavioral or
algorithmic level design. It provides a balance between the lower-level details of gate-level
design and the higher-level functionality of algorithmic design.
 At the RTL level, the design is described in terms of registers, data transfers between registers,
and combinational logic that operates on the data stored in registers.
 RTL designs are typically described using hardware description languages such as Verilog or
VHDL. These languages provide a formal and structured way to specify the behavior of digital
circuits at the register-transfer level.
 RTL description is synthesized into a gate-level netlist, which can be further optimized and
implemented.
 RTL Designing provides a structured and efficient methodology for designing complex digital
systems. Enabling easier verification, simulation, and implementation of digital designs.

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4.2 Combinational Logic Design
 In this method, the ALU is designed using combinational logic circuits, which directly map the
inputs to the outputs based on the selected operation.
 Each arithmetic and logical operation is implemented using appropriate combinational logic
circuits such as adders, subtractors, logic gates, and multiplexers.
 The inputs are directly connected to the logic gates and adder/subtractor circuits, and the outputs
are generated based on the selected operation and input values.
 Combinational logic designs do not have any internal memory elements, and the output is solely
determined by the current input values.
4.3 Logic Synthesis
Logic synthesis is a crucial step in the design flow of digital circuits, where a high-level behavioral
description of a circuit is transformed into an optimized gate-level representation. It involves the
translation of a design specified using a hardware description language (HDL) such as Verilog or VHDL
into a netlist composed of logic gates and flip-flops. Here's a basic overview of how it works:
4.3.1 High-Level Behavioral Description
The design process typically starts with a high-level behavioral description of the circuit's functionality.
This description specifies the desired input-output behavior of the circuit, often using an HDL.
Design
Specification
RTL
Design
Synthesis
Gate Level
Design
Layout
Fig. 4.1 Logic Synthesis Overview

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4.3.2 Technology Mapping
During logic synthesis, the behavioral description is mapped to a target technology library. The
technology library contains standard cells or components that represent the available logic gates, flip-
flops, and other elements in the chosen technology.
4.3.3 Netlist Generation
The logic synthesis tool analyzes the behavioral description and generates a gate-level netlist based on
the selected technology library.
4.3.4 Optimization
Logic synthesis includes various optimization techniques to improve the resulting netlist's performance,
area, and power consumption. It‟s aim to minimize the number of gates, propagation delays, eliminate
redundant logic, optimize power consumption.
4.3.5 Timing Analysis
Timing analysis is an integral part of logic synthesis. It performs timing analysis to estimate the circuit's
operating frequency and ensure that all timing constraints, such as setup and hold times, are met.
4.3.6 Technology Constraints
Logic synthesis considers technology-specific constraints, like the delay of gates, power consumption,
and area utilization. These constraints help guide the synthesis tool in making appropriate technology-
specific decisions during the mapping and optimization process.
4.3.7 Verification
After logic synthesis, the resulting gate-level netlist is typically subjected to verification using
simulation or formal methods. This helps ensure that the synthesized netlist behaves correctly and
matches the intended functionality specified in the high-level behavioral description.
4.3.8 Design-for-Testability (DFT):
Logic synthesis can also incorporate design-for-testability techniques, such as inserting scan chains,
built-in self-test (BIST) structures, or boundary scan (JTAG) features, to facilitate testing and fault
diagnosis in the manufactured circuit.

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Chapter 5
RESULT ANALYSIS
5.1 Definition
Basically result analysis refers to the process of examining and interpreting the outcomes or outputs of a
particular task, experiment, calculation, or simulation. It involves studying and evaluating the results to
gain insights, draw conclusions, and make informed decisions based on the obtained data.
5.2 Basic Block Diagram
Depending on the work, the generated basic block diagram can be figured out as;
8-Bit ALU
Input
A
Input
B
8
8
4
Control
8
Output
Fig. 5.1 Basic Block Diagram

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5.3 Truth Table of 8-Bit ALU
Here „A‟ and „B‟ denotes the two 8-bit binary data input and „S‟ denotes the selection line or control
line. Output‟s are in decimal form that human can understand better. Based on the selection line one of
the operation from those given is select and go for output.
Input (In Binary) Output (In Decimal)
a b s a+b a-b a*b a/b a%b a&b a | b a ^ b ~(a^b) ~a !a a&&b a || b
00001010
00000101
0000 15
0001 5
0010 50
0011 2
0100 0
0101 0
0110 15
0111 15
1000 240
1001 245
1010 0
1011 1
1100 1
Table 5.1 Truth table

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5.4 Timing Signal /Wave
Timing signal is an output which generates based on the clock pulse. After a specific given time it
breaks current running operation and jumps for running a new one. The generated timing signal of this
project is given below:
Fig. 5.2 Generated Timing Signal
5.4.1 Close Observation of Arithmetic Operation
Base Code Testbench Code
Fig. 5.3 Arithmetic operation close observation

19
5.4.2 Close Observation of Bitwise Operation
5.4.3 Close Observation of Logical Operation
Fig. 5.4 Bitwise operation close observation
Fig. 5.5 Logical operation close observation

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5.5 RTL Schematic Diagram
Schematic diagram of this ALU represents the circuit's components and their interconnections at a high
level. Here's a figure of generated schematic diagram during this project:
In this schematic a[7:0] and b[7:0] represents the 8- bit input operand. And O[7:0] represents the 8- bit
output of the ALU. S[3:0] represents the selection line which determines the specific operation to be
performed (e.g., addition, subtraction, logical AND, logical OR, etc.). The individual gates,
multiplexers, adders, and other components required for the ALU's operation are represented in a
simplified form.
Fig. 5.6 Schematic Diagram

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Chapter 6
MARKET RESEARCH AND ADAPTABILITY
The market adaptability of 8-bit Arithmetic Logic Units (ALUs) depends on various factors, including
the specific application requirements, technological advancements, market demand, and cost
considerations. Here's a detailed explanation of the market adaptability of 8-bit ALUs:
6.1 Legacy Systems
8-bit ALUs have a strong presence in legacy systems and retrocomputing enthusiasts. Many older
computer architectures and microcontrollers utilize 8-bit ALUs, and there is still demand for maintaining
and retrofitting these systems.
6.2 Embedded Systems
8-bit ALUs find extensive use in embedded systems, especially in applications with limited
computational requirements. They provide sufficient processing power for tasks such as sensor
interfacing, basic control functions, data acquisition, and small-scale data processing.
6.3 Low-Power Applications
In applications where power efficiency is critical, 8-bit ALUs can be favorable due to their relatively
lower power consumption compared to higher-bit counterparts. Battery-operated devices, IoT (Internet
of Things) devices, and energy-efficient systems can benefit from the use of 8-bit ALUs.
6.4 Education and Learning
8-bit ALUs play a significant role in educational settings for teaching digital logic, computer
architecture, and microcontroller programming. They offer a simplified and manageable platform for
students to understand fundamental concepts of ALUs and computational operations.
6.5 Technological Advancements
The market adaptability of 8-bit ALUs may evolve with technological advancements. As new
fabrication processes and design techniques emerge, the performance and efficiency of higher-bit ALUs
improve, narrowing the gap between the capabilities of 8-bit and wider ALUs.

22
Chapter 7
CONCLUSION, FUTURE WORK & REFERENCES
7.1 Conclusion
In conclusion, the design of a simple 8-bit Arithmetic Logic Unit (ALU) capable of performing
Arithmetic, Bitwise, and Logical operations is a valuable endeavor in the field of digital circuit design.
The ALU serves as a fundamental building block in various computational systems, offering the ability
to execute essential operations on binary data.
By successfully designing and implementing an 8-bit ALU, several key outcomes can be achieved.
Firstly, the ALU provides a compact and efficient solution for performing arithmetic operations such as
addition and subtraction on 8-bit binary numbers. It enables the manipulation of numerical data,
facilitating tasks ranging from basic calculations to more complex algorithms. Secondly, the ALU
supports bitwise operations, enabling the manipulation and comparison of individual bits within binary
data. This capability is essential in tasks such as bit shifting, bitwise AND/OR operations, and flag
manipulation, offering versatility and control over data at a granular level.
Furthermore, the ALU incorporates logical operations such as AND, OR, and XOR, allowing for the
evaluation of logical conditions and the generation of logical outputs based on binary inputs. This
functionality is crucial in decision-making processes, conditional branching, and boolean algebraic
manipulations. In conclusion, designing an 8-bit Arithmetic Logic Unit (ALU) is a challenging but
rewarding task in the field of digital design. The project explored the key components of designing an 8-
bit ALU, including the specifications, methodology, tools, and various gates and circuits that can be
used. However with careful planning, attention to detail and design process, we can create ALUs that
meet the needs of a wide range of applications for the future of digital design.

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7.2 Future Work
In future I am looking to design and optimize my ALU for better performance or lower power
consumption by,
 Reducing number of gates.
 Minimizing number of clock cycle.
 Using different types of logic gates.
In future I wish to build a physical 8-bit counter device with the help of ALU‟s.
7.3 References
 AC Computing Methodology for RF-Powered IoT Devices
(https://www.researchgate.net/figure/Block-level-diagram-of-the-8-bit-arithmetic-logic-
unit_fig5_331536471)
 Verilog syntax (https://www.chipverify.com/verilog/verilog-syntax)
 VLSI Design with Verilog
(https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm)
 Logic Gates - Building an ALU
(http://www.csc.villanova.edu/~mdamian/Past/csc2400fa13/assign/ALU.html)
 Verilog code for Arithmetic Logic Unit (https://www.fpga4student.com/2017/06/Verilog-
code-for-ALU.html)
 Verilog Coding Tips and Tricks (https://verilogcodes.blogspot.com/2015/10/verilog-code-
for-simple-alu.html)

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