14.design of area and power efficient digital fir filter using modified mac unit

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Design of Area and Power Efficient Digital FIR Filter Using Modified
MAC Unit
Abstract:
A novel scheme for the design of an area andpower efficient digital finite impulse
response (FIR) filter for digital signal processing (DSP) application’s is studied in this paper.
The key blocks of the filter are multipliers and adders, in which multiplier is the one which
occupies the major silicon area and consumes more power. In general, the multiplication
operations are performed by the shift and add logic. Most of the DSP applications demand faster
adders for its arithmetic computations. Carry Select Adder (CSLA) is a well-known adder for its
faster computation time. Recently, an efficient Carry Select Adder (CSLA) was proposed which
significantly reduce the area and power by eliminating the redundant logic gates at each bit level.
In this paper, we propose an area and power efficient FIR filter implementation using modified
multiply and Accumulate (MAC) unit. The performance analysis of the proposed FIR filter is
estimated with the MAC unit realized by the conventional adder and the modified carry select
adder as well. The proposed FIR filter architecture with length of 5-tap and 9-tap are developed
using Verilog HDL and implemented using SAED 90nm CMOS technology. The ASIC
synthesis results show that the Area Delay Product (ADP) of the proposed 5-tap and 9-tap filter
gains an improvement of 18.26% and 13.94%, respectively over the conventional method.
Similarly, the Power Delay Product (PDP) is improved by 16.80% and 12.54%, respectively.
Existing Method:

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The implementation of multiplier in FIR filters by decomposing the filter coefficients into
shift-and add operation has been studied well in the recent decades. In general, the multiplier
performs constant multiplication with the input samples as the filter coefficients are constant in
the digital filters. Several techniques for implementation of multiplier have been proposed and
categorized in to three classes. First, the sub-expression sharing (or elimination)aims to identify
the recursive pattern of the filter coefficient representation. Second, the difference methods
works on the basis of the difference exists between the coefficients and the new coefficients are
generated by summing anothercoefficient. Third, the algorithms for multiplier block which
computes the coefficients from the previous coefficients. Furthermore, lot of work focused on
Multiplier less digit-serial FIR filters implementation on FPGA. In, data transition power
diminution technique isemployed to reduce the dynamic switching power on adders and booth
multipliers for fir filter. In the authors have presented an algorithm which reduces the hardware
complexity of the multiplier block in the finite impulse response digitalfilters by reducing the
adder depth. Especially, in the trade-off due to digit-size has been studied with the usage of
direct multiplier blocks. In, a hybrid scheme has been proposed by combining Minimal
difference differential coefficients method with Common Sub-expression elimination in order to
achieve further reduction in complexity.
Proposed Method:
In this paper, we discuss the implementation of FIR filter using novel MAC unit realized
with the modified carry select adder proposed. The performance of 5-tap and 9-tap FIR Filter are
compared in terms of area, delay and power using the conventional MAC and modified MAC.
Applications:

3. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore
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1. Multimedia.
2. Communication Systems.
3. Mobile computing….etc.…
Advantages:
Reduces hardware Complexity.
System Configuration:-
In the hardware part a normal computer where Xilinx ISE 14.3 software can be easily
operated is required, i.e., with a minimum system configuration
HARDWARE REQUIREMENT
Processor - Pentium –III
Speed - 1.1 GHz
RAM - 1 GB (min)
Hard Disk - 40 GB
Floppy Drive - 1.44 MB
Key Board - Standard Windows Keyboard
Mouse - Two or Three Button Mouse

4. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore
www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457
Monitor - SVGA
SOFTWARE REQUIREMENTS
 Operating System :Windows95/98/2000/XP/Windows7
 Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for
Synthesis and Hard Ware Implementation
 This software’s where Verilog source code can be used for design
implementation.