1. Improvement of Substrate and Package Warpage by Copper Plating Process Optimization
Omar Bchir1
, Houssam Jomaa1
, Chin Kwan Kim1
, Layal Rouhana1
, Kuiwon Kang2
, Milind Shah1
, Steve Bezuk1
Qualcomm Technologies, Inc.
1
5775 Morehouse Drive, San Diego, CA 92121 USA
2
POBA Gangnam Tower, 119, Nonhyeon-dong, Gangnam-gu,Seoul, KO 135-820 (Korea)
obchir@qti.qualcomm.com, 858-658-2813
Abstract
High substrate warpage can lead to unacceptable yield
loss during chip attach in assembly, and cause high yield
fallout during package mount on the circuit board. For the
first time, through this work, the electrolytic copper (Cu)
plating process in substrate manufacturing was shown to
contribute significantly to package warpage. For a 14x14mm
package, reducing the Cu plating rate (within the
manufacturing operating window) resulted in 21% package
warpage reduction, while a change in Cu plating solution
provided an additional 6% reduction (total 27% reduction).
Hence the Cu plating process and solution must be carefully
scrutinized to minimize package warpage, specifically for thin
packages (<1mm) where Cu stresses become a large
contributing factor.
Introduction
As the industry moves to thinner packages, control of
package warpage is an increasing area of concern. The
substrate is a large factor in determining overall package
warpage performance. High substrate warpage can lead to
unacceptable yield loss during chip attach in assembly, and
cause high yield fallout during package mount on the circuit
board.
Substrate warpage improvements are typically approached
through modification of dielectric material properties (such as
CTE, Tg, modulus), layer thicknesses (core, prepreg, solder
resist and Cu thickness), and Cu areal density per layer. An
overlooked factor in the warpage improvement effort is the
impact of the electrolytic Cu plating process. Electroplated
Cu thin films tend to have porous grain boundaries, wherein
grain boundary volume is strongly dependent on
electroplating conditions and subsequent thermal processing
[1]. During thermal processing, Cu grains grow and merge,
eliminating grain boundaries; Cu deposits with larger grain
boundary volume shrink more. The residual stress in the
initial deposit, coupled with shrinkage during subsequent
thermal processing, strongly impacts the warpage response of
the substrate and package. This is compounded by the
inherent front-to-back Cu density imbalance which is typical
in substrate design.
Test Device and Processing Description
The first step in the analysis was to check the magnitude
and mode of stress in the deposited Cu. This was done using
deposit stress test strips and a Deposit Stress Analyzer system
from Specialty Testing & Development Co. (York, PA,
USA). Test strips were plated in a bench-top electrolytic
plating cell, using various chemistries and plating current
density conditions of interest. After plating, the thickness of
the deposited Cu, as well as the increments of spread between
the test strip legs, were measured. These values, along with
the strip calibration constant and direction of spread, were
used to determine deposit stress magnitude and mode
(compressive vs. tensile).
Next, substrates were manufactured for use in warpage
testing. Substrates were built in panel format, using a typical
electrolytic copper plating configuration (Figure 1). The inner
layers on the front and back of the panel were plated
simultaneously in an initial step. The outer layers on the front
and back of the panel were also plated simultaneously in a
subsequent step.
Figure 1. Typical setup for substrate electrolytic Cu
plating process used in this evaluation.
Two different substrate designs, both with 14x14mm body
size, were used for this evaluation. The first design (DES1)
used a 4-layer substrate with 18um Cu thickness per metal
layer, a 100µm core with CTE <12ppm/°C, and was
manufactured by a first substrate supplier. The second design
(DES2) used a 4L substrate with 18um Cu thickness per metal
layer, a 100 µm core with CTE <5ppm/°C, and was
manufactured by a second substrate supplier. The substrate
material sets and layer thicknesses were fixed for each design;
the only variables explored in this evaluation were the
electrolytic Cu plating solution and plating current density in
amperes/dm2
(ASD). A total of three different electrolytic Cu
plating solutions were tested: solutions A and B (on DES1)
and solutions B and C (on DES2). Several different ASD
skews were also tested on each substrate design.
The substrates were then assembled into overmolded PoP
(package on package) bottom packages. The assembly
material set and thickness was fixed for each design. These
packages were then used to conduct warpage evaluations.
Unit-level high temperature package warpage data was
collected using an Akrometrix Shadow Moiré tool and 100
lines per inch (LPI) grating. HT warpage data was collected
using a peak temperature of 260C.
978-1-4799-2407-3/14/$31.00 ©2014 IEEE 1396 2014 Electronic Components & Technology Conference

2. Cu Deposit Stress Results
Deposit stress analysis results generally indicated
compressive stress in the as-plated Cu, with stress
transitioning to tensile mode after either long sit times at room
temperature or post-plating bake. Figure 2 shows example
photos of plated test strips before and after baking. The
change in stress state after baking or long sit times is due to
the metastable nature of the deposited Cu grains, which tend
to coarsen into larger grains with time to eliminate grain
boundaries and reduce overall interfacial energy of the
system. This phenomenon of a compressive deposit relaxing
to a tensile state has been reported previously for electroless
and electroplated Cu films [2,3].
Figure 2. Example Cu deposit stress strips measured (a)
after plating (compressive mode) and (b) after baking (tensile
mode) at 200°C for 2 hours.
For a given plating current density, the electrolytic Cu
plating solution impacted the magnitude and evolution of
stress in the plated deposit. Figure 3 shows the impact of
successive thermal treatments on the evolution of Cu stress
plated by solution A vs. solution B. The as-plated Cu stress is
compressive for both chemistries, but the magnitude is higher
for solution B than for solution A. After aging for 6 hours at
room temperature (RT), the deposit from solution A has
already relaxed to tensile mode, while the deposit from
solution B has relaxed to a lesser degree, and is still in
compressive mode. After baking, deposits from both solution
A and B are in tensile mode; their respective stress levels
remain constant after an additional 10 days aging at RT.
Between 10 and 30 days aging at RT, the stress drifts upward
for samples from both plating solutions, but is more
significant for solution A (67% increase) than B (15%). This
continued relaxation after 30 days is indicative of the degree
of residual stress in the as-plated Cu, and suggests that the
stress state in the Cu layers of the substrate continues to
evolve well after manufacturing is completed. The higher
degree of relaxation for Cu from solution A suggests that
deposits from this solution have more residual stress than
those from solution B, and therefore have lower metastability
(i.e. more prone to grain coarsening). Note that the surface of
the plated Cu is fully exposed in the deposit stress coupon,
allowing the Cu to diffuse/shrink freely to minimize the
overall energy of the system. The Cu layers in the substrate
are constrained by neighboring dielectric layers, however,
which would inhibit the rate and degree of change from
compressive toward tensile mode. The final stress state in the
substrate’s Cu would therefore be more strongly influenced
by the as-deposited stress state.
Figure 3. Impact of plating solution and thermal history
on stress in plated Cu at a fixed current density.
For a given plating solution, the plating current density
also impacted the magnitude and mode of stress in the plated
deposit. Fundamentally, increasing the plating current density
leads to reducing the size of the deposited grains [1], wherein
the smaller grains are less thermodynamically stable [4].
Smaller grains have more grain boundaries per unit volume of
deposited Cu, and higher plating current density should
therefore give rise to higher compressive stress.
Figure 4. Impact of electrolytic Cu plating current density on
stress in the deposit for as-plated and post bake / aging
conditions.
Interestingly, however, the time zero data in Figure 4
shows that increasing the current density value results in a
shift from more compressive to less compressive stress in the
as-plated deposit. This trend was confirmed for multiple
vendor chemistries (not shown), as was the shift to tensile
mode after baking for all current densities. For the time zero
deposit, the reduction in compressive stress with increasing
current density is counter intuitive, and is believed to be due
to compressive and tensile regions coexisting in the deposit,
coupled with limitations of the deposit stress analyzer
method. This method provides “net” deposit stress results,
which can vary depending on the ratio of compressive to
tensile stresses in the plated deposit. A reduction in net
compressive stress could indicate that compressive stress is
indeed lower, or that the ratio of the deposit under tensile
stress has increased. Our hypothesis is that the Cu grains
nucleating at the deposit surface are under compressive stress,
and grain coarsening and relaxation into tensile mode occurs
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3. in part of the bulk layer as plating continues. Figure 5 shows
a pictorial explanation. At low plating current density, the
initially deposited Cu grains would be relatively large and
stable. As plating continues, these grains would continue to
nucleate at the deposit surface, while a relatively small
percentage of grains in the underlying bulk Cu would be
coarsening and relaxing into tensile mode. At high plating
current density, the initial deposited grain size is small,
increasing the compressive nature of the surface deposit, and
increasing the driving force for grain coarsening and
relaxation in the bulk of the Cu. Similarly, a transition from
small grains at the as-plated Cu surface to larger grains in the
bulk layer was reported previously [5].
Figure 5. Schematics depicting impact of plating current
density on initial grain size and final grain size/stress state
after full layer plating.
Package Warpage Results
Results for DES1 (Figure 6) show the impact of plating
solution and current density magnitude on package warpage.
For solution A, reduction of plating current density on inner
and outer layers (leg 1 vs. 2) provides an 11m /19m
mean/max warpage reduction. For solution B, reduction of
plating current density on inner and outer layers (leg 3 vs. 4)
provides a 6m reduction in both mean/max warpage. At
higher plating current density, a change in plating chemistry
from solution A to B (leg 1 vs. 3) provides a 12m /26m
mean/max warpage reduction. At lower plating current
density, a change in plating chemistry from solution A to B
(leg 2 vs. 4) provides a 7m /13m mean/max warpage
reduction. Overall, a change in plating chemistry from
solution A to B, coupled with a reduction in plating current
density (leg 1 vs. 4), provides a very substantial 18m
/32m mean/max warpage reduction. Plating solution B with
lower plating current density on the inner/outer layers was
demonstrated to have the best warpage performance on DES1.
While plating solution and current density strongly affected
warpage magnitude for DES1, they had no impact to warpage
shape change (i.e. smiling vs. crying) with temperature, as per
the signed warpage graph in Figure 6.
Figure 6. DES1 high temperature warpage results
(unsigned and signed) for Cu plating solution and ASD skew
builds.
Results for DES2 (Figure 7) show the impact of plating
solution, current density magnitude, and current density
balancing (inner vs. outer layers) on package warpage. At
lower plating current density, a change in plating chemistry
from solution C to B (leg 5 vs. 8) provides a 14m /9m
mean/max warpage reduction. For solution B, using a higher
current density on the inner vs. outer layers (leg 6 vs. 7)
provides a 7m /8m mean/max warpage reduction. As
with DES1, solution B with lower plating current density on
the inner/outer layers was demonstrated to have the best
warpage performance on DES2. Moreover, the data indicates
the importance of balancing plating current density on inner
vs. outer layers. Use of current density on the outer layers
which is equal to or lower than that on the inner layers was
better for warpage.
While plating solution and current density strongly
affected warpage magnitude for DES2, they had no impact to
warpage shape change (i.e. smiling vs. crying) with
temperature, as per the signed warpage graph in Figure 7.
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4. Figure 7. DES2 high temperature warpage results
(unsigned and signed) for Cu plating solution and ASD skew
builds.
Conclusions
Results of the analysis show that choice of substrate
electrolytic Cu plating solution has significant impact on the
magnitude of package warpage. The influence of Cu plating
solution on warpage is related to the resulting grain size
distribution and stress state deposited from a given chemistry.
Additives such as levelers and brighteners are used in the
plating solution to control deposition rate across features on
the panel. Additives are intended to, in part, foster hydrogen
evolution, change the electrode potential at the plating
surface, and brighten the deposit surface [6]. These same
additives (or fragments thereof) can be co-deposited as
impurities into the Cu layer, and have been shown to strongly
impact residual stress and grain coarsening behavior of the Cu
deposit [7]-[9]. The additive makeup and chemistry in a
given plating solution can therefore influence the deposited
grain size, the amount of impurities and residual stress in the
plated Cu, the rate/extent of grain coarsening, and the overall
package warpage. This is evident in Figure 3, which shows a
difference in the initial deposit stress and rate of stress change
for solution A vs. B.
Based on warpage data from DES1 and DES2, Cu plating
solution B provides lower package warpage. Linking Cu
stress and warpage results together for plating solution B
(Figures 3, 6 and 7), we believe that higher compressive stress
(and higher metastability) in the as-plated Cu, coupled with
slower change to tensile mode, provides lower package
warpage.
Results from this study also show that electrolytic Cu
plating current density has significant impact on the
magnitude of package warpage. For both DES1 and DES2,
reducing the plating current density for a given plating
solution led to substantial reduction in package warpage
(Figures 6 and 7). As mentioned previously, an increase in
the plating current density causes a reduction in the deposited
grain size [1], hence a reduction in current density would lead
to larger deposited grains. Larger grains would mean
reduced grain boundary volume, less “shrink” in the Cu layer
as it relaxes to tensile mode, and potentially lower residual
stress in the Cu. While reducing current density improves
package warpage, it negatively affects plating process
throughput in high volume manufacturing. Since current
density is related to throughput and package warpage, a
balance must be maintained to ensure good warpage and good
plating productivity. Figure 8 depicts the target operating
range for current density to balance warpage performance
against throughput, and the associated as-deposited Cu stress.
Figure 8. Proposed operating range for Cu plating current
density to control package warpage.
Apart from the plating current density magnitude,
balancing of the current density used to plate the inner vs.
outer layers of the substrate was also important for warpage.
Results from DES2 (legs 6 vs. 7) show that use of current
density on the outer layers which is equal to or lower than that
on the inner layers was better for warpage. Substrate designs
typically have an inherent front/back Cu density imbalance,
which when coupled with higher current density on the outer
layers, appears to exacerbate warpage issues. If we assume
that the center of the core layer is the substrate’s neutral axis
(Figure 9), we can consider the moment caused by residual
stress in each Cu layer based on the following relation:
M = F * d
where M is the moment, F is the force and d is the distance
from the neutral axis to the Cu layer of interest.
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5. Figure 9. Schematic showing moment equation as applied
to Cu layers in the substrate.
With equivalent residual stress in all Cu layers
(F1=F2=F3=F4), the outer layers by definition have a larger
moment than the inner layers, due to their greater distance
(d1,d4) from the neutral axis. Higher residual stress in the
outer layers (F1,F4), coupled with larger distance to neutral
axis (d1,d4), would cause more curling/warpage. Higher
residual stress on the inner layers (F2,F3) has less impact to
warpage, as the closer proximity to the neutral axis (d2,d3)
counterbalances the force in the moment equation. By this
logic, and based on empirical results, we believe that use of a
plating current density on the outer layers which is less than
or equal to the inner layers is best for warpage.
One typical approach to control package warpage is to
bake the substrate before assembly to eliminate residual
stresses. Prior testing on DES1 showed this to have no
impact on package warpage. While baking the substrate may
reduce residual stress in the Cu layers (through Cu shrink),
this stress would be transferred into neighboring dielectric
layers, and is therefore not eliminated from the substrate.
Hence baking a substrate which already has a Cu areal density
imbalance (by design) is not expected to provide a benefit for
package warpage.
From initial warpage modeling work, the magnitude of the
net deposit stress values reported above were considered to be
small, having little impact on simulated warpage behavior of
the final substrate. The empirical warpage results, however,
conclusively show that the residual stress state in the Cu is
important for package warpage. The sources of this
disconnect between modeling and empirical data is unclear at
this time, and will be explored in future work.
Based on the complete analysis, the following variables in
the substrate Cu plating process proved to be critical for
package warpage control:
1. Cu plating solution chemistry
2. Magnitude of Cu plating current density
3. Cu plating current density balancing on inner vs.
outer layers
For warpage-sensitive packages, the above variables should
be carefully considered and evaluated to determine the best
operating window for a given package/substrate design.
Acknowledgments
The authors would like to thank Nancy Bailey at
Qualcomm for her work to standardize our warpage
measurement methodology, and our substrate and assembly
partners for executing the builds in this study. We would also
like to thank Qualcomm’s management team for their support
of this work.
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