Recently, with new hardware architectures such as Reconfigurable Match Tables and languages such as P4, the Software Defined Networking community has started to bring linerate dataplane programmatic flexibility inside switching chipsets. Nowadays, the most diffused approach to packet manipulation is to have a pipeline of match/action stages in which the packet”flows” while being modified according to match events. Great effort has been put on improving the programmability of the match engine of the hardware architectures that implement this sort of pipeline, but very few attempts has been made to make the actions truly programmable, remaining stuck with aconcept of ”atomic” action. We will see how a domain-specific HW architecture, called Packet Manipulation Processor (PMP), is able to efficiently support micro-programs implementing such programmable actions. About the author: Marco Spaziani Brunella is a Researcher for CNIT at University of Rome Tor Vergata. In the last year, he focused on CPU architectures suitable for SDN and hardware-implementable data structures such as Cuckoo hash and Bloom filters for networking.