Rf power gating a low power technique for adaptive radios Rf power gating a low power technique for adaptive radios Rf power gating a low power technique for adaptive radios
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Rf power gating a low power technique for adaptive radios
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RF Power Gating: A Low-Power Technique for
Adaptive Radios
Abstract:
In this paper, we propose a low-power technique, called RF power gating, which consists in
varying the active time ratio (ATR) of the RF front end at a symbol time scale. This technique is
especially well suited to adapt the power consumption of the receiver to the performance needs
without changing its architecture. The effect of this technique on the bit error rate (BER)
performances is studied for a basic estimator in the specific case of minimum-shift keying
signaling. A system-level energy model is also derived and discussed to estimate precisely the
power reduction based on the characteristics and the power consumption of each block. This
model allows highlighting the different contributors of the power reduction. The BER results and
the energy model are finally merged to determine the best ATR meeting the design constraints.
Applying this technique to the IEEE 802.15.4 standard, this paper shows that an ATR of 20% is
a good tradeoff to meet the packet error rate constraint while maximizing the energy reduction
ratio. Using typical block power consumptions, an energy reduction ratio around 20% can be
reached. Even better energy reduction ratios (∼60%) are also achievable when most of the blocks
are power-gated. The proposed architecture of this paper analysis the logic size, area and power
consumption using Xilinx 14.2.
Enhancement of the project:
Existing System:
Some techniques have been proposed toward the reduction of the RX power consumption, the
main solution proposed by adaptive radios is to leverage the emitted power of the transmitter
(TX) to adapt the TX/RX system to the quality of the communication channel and save a
substantial amount of power at the TX level. However, saving power at the RX level is of major
concern for some wireless sensor network or Internet of Things applications. For example, in a
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star network topology, a main node is usually used to manage the network and is required to
broadcast some updates to all the end nodes. In those cases, the main node is usually supplied by
the grid power, while the end nodes are battery powered (see agriculture field monitoring or
smart meters applications), and it is more efficient to increase its TX power while reducing the
RX power of the multiple end nodes. To do so, with narrow-band RXs, recent works mainly
leverage the tradeoff between the power consumption of RX circuits and their linearity or noise
factor (NF). While a few works use this tradeoff to design block circuits, extending it at the
system level requires scalable devices and still belong to the simulation domain. Although the
narrow-band RXs do not benefit from duty-cycle modulation as impulse-radio ultra wide band
(IR-UWB) do, some recent works consider duty-cycling some parts of the narrow-band RXs.
The baseband circuits are duty-cycled, both LNA and mixer are intermittently shut down. More
recently, Pons et al. proposes to reduce the RX power consumption by leveraging the analog-to-
digital converter (ADC) sampling frequency and by allowing sampling points as close as
possible, enabling the use of power-gated ADC. Similarly, we propose to extend this power
adaptability to the whole RF RX.
Disadvantages:
Power consumption is high
Proposed System:
RF POWER GATING
The RFPG technique is a power management technique based on shutting down RF modules
inside a symbol time. This principle is widely used for digital circuits by enabling clock-gating
or by disabling the parts of the design. The RFPG extends this principle to the RF front end.
Basically, as shown in Fig. 1 for the MSK modulation, inside a time symbol, the direction of the
transmitted signal phase remains the same. Consequently, for a given noise environment, it
should be possible to decode the data from samples of the received signal taken during a fraction
of the symbol time at the expense of degraded performances. Assuming it is possible, the parts of
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the RF RX could be shut down outside this portion of the symbol time called the sampling
window.
Fig. 1. Phase direction of a binary CPFSK modulation, where m is the modulation index. In the case of an
MSK modulation, m = 0.5.
the shorter the sampling window is, the longer the RF components are turned OFF and then the
less power is consumed. However, as explained in the rest of Section II, choosing a smaller
sampling window degrades the sensitivity of the RX. In other words, considering the noise
provided by the communication channel and the analog parts, the sampling window width must
be bounded to ensure a certain BER under some specific signal-to-noise ratio (SNR) conditions.
RF Front End
This is deals with all the RF front-end components of the RX (see Fig. 2) placed before the ADC,
including the LNA, the mixer, the filter, and the phase-locked loop (PLL). In the rest of this
paper, these components are called analog parts. Each analog part, indexed by i, is represented
by four parameters: the active and inactive currents drawn ION,i and IOFF,i , and the settling
and shutting down times t↑,i and t↓,i . These times are defined in the following.
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1) t↑,i is the necessary time for the supplying current of an analog part i starting from IOFF,i
to remain in a 2ρ(ION,i − IOFF,i)-wide interval centered in ION,i .
2) t↓,i is the necessary time for the sinking current of the analog part i starting from ION,i to
remain in a 2ρ(ION,i − IOFF,i)-wide interval centered in IOFF,i .
Fig. 2. Example of an RFPG zero-IF front-end architecture.
Analog-to-Digital Converter (ADC)
In this section, the relationship between the sampling time width tw and the consumption of the
ADC is given. Using the work provided in that collects thousands of ADC characteristics since
1974, a model of the active power consumption of an ADC can be bounded by the Walden slope
and the thermal slope expressed by
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Advantages:
Power consumption is reduced
Software implementation:
Modelsim
Xilinx ISE