1. PROJECT REPORT
(Project Semester January-April 2015-16)
Implementation of Costas Loop for BPSK demodulation on a
Microsemi Actel FPGA (Field Programmable Array) for carrier
signal of 8/16 KHz and data rate of 2/4 kbps
Submitted By
Devanshi Upadhyaya
(120070102152)
Registration No. : T160051
Communications Systems Group
Under the supervision of
Mr. Aditya Ganesh Mr. Kuldeep Choudhary
ENGR SE Asst. Professor
CSG, ISAC Deptt. Of ECE, DIT
Department of ECE & AEI
DIT University, Dehradun
Uttarakhand-248009
April-2016
2. DECLARATION
I hereby declare that the project work entitled (“Implementation of Costas Loop for BPSK
demodulation on a Microsemi Actel FPGA (Field Programmable Array) for carrier signal of 8/16
KHz and data rate of 2/4 kbps”) is an authentic record of my own work carried out at CSG, ISAC
as requirements of Industry Internship project for the award of degree of B.Tech, DIT
University, Dehradun under the guidance of Mr. Aditya Ganesh and Mr. Kuldeep Choudhary
during January to April, 2016.
Devanshi Upadhyaya
Regis. No. T160051
Date: April 28, 2016
Certified that the above statement made by the student is correct to the best of our knowledge
and belief.
Mr. Aditya Ganesh Mr. Kuldeep Choudhary
ENGR SE Asst. Professor
CSG, ISAC Dept. Of ECE, DIT
3. Acknowledgment
The successful completion of this project work is due to the encouragement and guidance
provided by a lot of people without whose help this would have been difficult.
I wish to express my heartfelt gratitude to Mr. Yatendra Mehta, Group Director, CSG
(Communication Systems Group), ISRO Satellite Centre for his support in doing the project
work.
The execution of my project work would have been impossible without the constant
encouragement and proficient guidance of both my external and internal guides Mr. Aditya
Ganesh, Scientist/Engineer ‘SE’, CSG and Mr. Kuldeep Choudhary, Asst Professor, DIT. They
helped me in design work, testing and also guided in integration testing of the code. They took
out time from their busy schedules to discuss and solve a lot of my doubts.
I express my sincere gratitude towards Dr. Sandeep Sharma, HOD, Deptt. Of ECE, DIT for
providing the right academic guidance.
I would also like to thank Mr. Gaurav Upadhyay, Scientist ‘SD’, DHSG and Mrs. Sangita Sahu,
Scientist ‘SC’, DHSG who helped a lot in the coding and debugging.
Finally, I would like to thank my project partner Prabhpreet Dua who was always helpful with
the project. Thanks to all the individuals who have directly or indirectly helped me in the
completion of this project.
4. CERTIFICATE
This is to certify that this thesis work titled
Implementation of Costas Loop for BPSK demodulation on a Microsemi Actel
FPGA (Field Programmable Array) for carrier signal of 8/16 KHz and data
rate of 2/4 kbps
is a bonafide record of the work done by
Devanshi Upadhyaya
Registration No. T160051
In partial fulfillment of the requirements for the award of the degree of Bachelor of Technology
in Electronics and Communication Engineering under Dehradun Institute of Technology,
Dehradun and the same has not been submitted elsewhere for the award for any other degree.
Guide Name: Mr. Aditya Ganesh,
Designation: Scientist/Engineer ‘SE’,
Communication Systems Group
Industry Name: ISRO Satellite Centre
City: Bangalore
5. CONTENTS
1. ORGANISATION OVERVIEW...................................................................1
1.1 INTRODUCTION.............................................................................2
1.2 EVOLUTION OF ISAC.....................................................................2
1.3 VISION, MISSION AND OBJECTIVE..................................................3
1.4 ORGANISATION STRUCTURE..........................................................4
2. PROFILE OF THE PROBLEM...................................................................6
3. BACKGROUND........................................................................................9
3.1 GENERAL DESCRIPTION..............................................................10
3.2 PHASE SHIFT KEYING..................................................................11
3.3 PSK DEMODULATION...................................................................11
3.4 CARRIER RECOVERY...................................................................12
4. CONCEPT VERIFICATION USING MATLAB...........................................13
4.1 BPSK MODULATOR......................................................................14
4.2 DEMODULATOR...........................................................................15
5. SOFTWARE DESCRIPTION....................................................................17
5.1 OVERVIEW..................................................................................18
6. 5.2 FEATURES...................................................................................19
5.3 SYNPLIFY PRO ME.......................................................................19
5.4 MODEL SIM ME...........................................................................21
5.5 FPGA DESIGN FLOW IN LIBERO....................................................22
6. ANALYSIS OF COSTAS LOOP.................................................................25
6.1 INTRODUCTION...........................................................................26
6.2 NCO............................................................................................28
6.3 ARM FILTER...............................................................................29
6.4 LOOP FILTER..............................................................................30
7. DESIGN OF COSTAS LOOP....................................................................31
7.1 PROCEDURAL DESIGN.................................................................32
7.2 NCO............................................................................................34
7.3 ARM FILTER...............................................................................34
7.4 LOOP FILTER..............................................................................35
8. SOURCE CODE......................................................................................36
8.1 TOP ENTITY (COSTAS LOOP)........................................................37
8.2 ARM FILTER...............................................................................37
7. 8.3 LOOP FILTER..............................................................................39
8.4 NCO............................................................................................40
9. CONCLUSION AND SCOPE FOR FUTURE WORK....................................41
REFERENCES...........................................................................................43
APPENDICES............................................................................................44
A1 IMPLEMENTATION ON A FPGA BOARD...................................................44
A1.1 FIELD PROGRAMMABLE GATE ARRAYS ................................44
A1.2 BENEFITS OF FPGA TECHNOLOGY.............................................44
A2 GLOSSARY...........................................................................................47
9. 1.1 Introduction
ISRO Satellite Centre is the lead centre of the Indian Space Research Organization (ISRO)
responsible for design, development, assembly & integration of communication, navigation,
remote sensing, and scientific and small satellite missions.
The specialized teams of scientists, engineers and technicians of ISAC have built more than 75
complex & advanced satellites for various applications in areas of telecommunications,
television broadcasting, VSAT services, tele-medicine, tele-education, navigation, weather
forecasting, disaster warning, search and rescue operations, earth observations, natural resource
management, scientific and space science etc.
With the objective of taking the benefits of space technology to the length & breadth of the
society, ISAC is actively involved in creating cost-effective space infrastructure for the country.
1.2 Evolution of ISAC
1. The establishment of Thumba Equatorial Launching Station (TERLS) in 1963 and the
Experimental Satellite Communication Earth Station (ESCES) in 1967 was the prodigious
precursors to Space activities in the country.
2. Activities relating to satellite technology started in the right earnest at Satellite Systems
Division at Space Science & Technology Centre, Trivandrum in the late sixties.
3. Later when a conscious decision emerged in 1972 to build the first Indian Satellite 'Aryabhata'
the scene shifted to Bangalore with the formulation of the Indian Scientific Satellite Project
(ISSP).
4. The Indian Institute of Science campus initially housed the project activities until it moved to
the industrial sheds at Peenya.
5. It was here that a handful of engineers and technicians fresh from the Universities sowed the
first seeds of satellite technology in the country.
10. 6. With practically no prior art existing within the country, and with sparse infrastructure put
together from scratch, this young team developed the first Indian Satellite ARYABHATA in the
make shift industrial sheds at Peenya, Bangalore.
7. With the success of the ARYABHATA mission, the fledgling space activity soon developed
into a full-fledged programme with national priorities.
8. Thus was born the ISRO Satellite Centre (ISAC) in 1976. In 1984 the Centre moved to the
present 32 acre campus at Old Airport Road, Vimanapura in Bangalore.
9. To cater to the growing need of satellite for various applications, ISRO Satellite Integration &
Testing Establishment (ISITE) was established in 2006 in a 110 acre campus which is about 8
km away from the present campus.
10. ISITE has a large clean room and state-of-the-art electronics fabrication and test facilities
under one roof for the assembly, integration and testing of communication satellites.
1.3 Vision, Mission and Objective
VISION
To harness space technology for national development, while pursuing space science research
and planetary explorations.
MISSION
1. Design and development of satellites and related technologies for providing access to space
2. Research and development in satellite related technologies
OBJECTIVE
The objective of ISRO Satellite Centre is building state of the art satellites and related
technologies in the area of communication, navigation, earth observation, meteorology, space
science and planetary exploration etc in a cost effective manner for the socio-economic
development of the country.
11. 1.4 Organization Structure
The Centre is functionally organized into technical areas, facilities Group, management areas
including programme management & planning Group and administration area. The Centre is
headed by Director and the heads of each Functional Area directly report to Director of the
Centre. To optimally utilize the limited resources and simultaneously execute multiple projects,
matrix style of organization is adopted in the Centre.
Mechanical Systems Area - responsible for design, analysis, fabrication, testing and
delivery of mechanical hardware of all Spacecraft projects.
12. Communication & Power Area - responsible for design, development, fabrication and
testing of spacecraft RF systems and electrical power systems.
Controls & Digital Area - responsible for onboard computer design, Control dynamics,
digital systems like Telemetry, Telecommand, Storage systems, data handling, ground
encoders and research in Space Science and Instrumentation.
Integration & Checkout Area - responsible for complete mechanical and electrical
integration of spacecraft, EMI control plans, spacecraft ground check out systems support
and integrated spacecraft level testing, final operations at launch complex.
Reliability & Quality Area - responsible for reliability and quality assurance of all
spacecraft hardware and space qualified component management including Hybrid Micro
Circuits (HMC) development.
Mission Development Area - generates exhaustive mission plan and operation documents,
selects orbit and carry out attitude analysis, navigation software development and support
Ground segment for navigation programme. It is responsible for establishment and
management of Centralized IT infrastructure of the centre.
Systems Production Area - draws up elaborate plan for production of standardized
electronics hardware and implements it through in-house facilities and external vendors.
Facilities Group - responsible for the establishment, management and maintenance of
facilities/infrastructure to cater to the need of fabrication, assembly and testing of spacecraft
from component to system level to spacecraft level. It also supports other activities like
Photo copying, Electronic Maintenance and Internal Photography.
Planning Group - provides interface between the various technical area, the administrative
divisions and the management and outside agencies.
GEOSAT Programme, IRS Programme & Small Satellites Programme, Microwave
Remote Sensing Satellite Programme and Satellite Navigation Programme - responsible
for definition, conceptualization, design and building of all geostationary satellites, earth
observation satellites and navigation satellites to suit various applications respectively.
Systems Engineering, Budget and Planning, Configuration & Data management etc are the
core responsibilities of each programme management office.
Administration Area - supports activities related to construction & maintenance, purchase,
stores, accounts, general administration, canteen facilities and medical facilities.
14. The present telecommand system uses a BPSK demodulator onboard satellite for demodulating
command signals. The BPSK demodulator uses a coherent demodulation technique to
demodulate the incoming PSK signals. The coherent demodulation technique requires at
receiver a reference carrier which is in phase with the transmitted carrier for optimum
demodulation. It also requires a reference clock, which is in phase with the transmitted
clock for making correct data decisions. The PSK modulation technique is a suppressed
carrier system, i.e., the spectrum of PSK modulated signal does not have carrier or clock
component for coherent demodulation. The carrier and clock components have to be
generated at the receiver from the signals received. The process of recovering or
generating the carrier from the received signal is called ‘carrier recovery process’ and the
process of recovering clock from the received signal is called ‘clock recovery’ or ‘symbol
timing recovery’.
The Costas Loop is often used to extract the coherent carrier. Here, an optimum method is
proposed to realize the costas loop based on FPGA. The costas loop is studied in analog domain
LPF (Low Pass Filter), LF (Loop Filter) and VCO (Voltage Controlled Oscillator). Then it is
implemented in digital domain using digital multiplier and NCO (Numerically Controlled
Oscillator) replacing the VCO. The functional simulation is accomplished in VHDL code on
Libero.
Modulation is the process by which some characteristic of a carrier is varied in accordance with a
modulating wave (signal). At the receiver end, demodulation must be accomplished to recognize
the signals. The process of deciding which symbol was transmitted is referred to as a detection
process. Typically, the receiver generates a signal that is phase-locked to the carrier. Binary-
phase shift keying (BPSK) may use a coherent receiver for this purpose. Coherent detection and
demodulation requires the utilization of synchronization systems that extract carrier phase and
frequency information from the received signal. Phase and frequency are two parameters used by
synchronization systems, such as Phase-Locked Loops (PLL) to track, acquire and synchronize
to the carrier of the received signal. Making use of additional components, PLLs can be used
directly to demodulate a signal when the signal contains a positive average energy at its carrier
frequency. The carrier is used in the receiver to synchronize to, as the residual energy at carrier
frequency is considered to be wasted energy as it does not transmit any data. In practice,
techniques that conserve power are of interest, hence communications systems use suppressed
15. carrier modulation/demodulation techniques, which do not require a residual energy at the carrier
frequency. Using suppressed-carrier modulation techniques, present a problem for PLLs, since in
the absence of the carrier, PLLs cannot track, acquire and synchronize to the received signal.
Therefore, another synchronization system must be used instead. An example of such a system is
the Costas loop. The primary focus of this work is to study and implement Costas loop as a
demodulation technique for digital communication receivers.
The Costas loop is a synchronization system that was first introduced by John Costas in 1956 to
achieve phase tracking, acquisition, synchronization and demodulation of double-sideband
suppressed-carrier AM signals. The Costas loop is able to obtain the phase and frequency
information of the modulated carrier and achieve phase tracking, acquisition and synchronization
to this extracted carrier while demodulating and extracting the data contained in the received
signal. Although the original intent of the Costas loop was to track and demodulate double-
sideband suppressed-carrier AM signals, it can very well be used to demodulate other
suppressed-carrier modulation techniques. Another modulation technique for which the Costas
loop is readily used without modifications is BPSK. The truth of this statement lies in the fact
that BPSK signals can be expressed and demodulated as double-sideband suppressed-carrier AM
signals. Other applications of the Costas loop are demodulation of QPSK (Quadrature Phase
Shift Keying), M-ary PSK, and OQPSK (Orthogonal QPSK).
The Costas loop can be considered to be a variation of a PLL system. Costas loop theory
describes the system as two phase-locked loops operating in phase quadrature to each other. The
performances of traditional analogy Costas loop are affected because of the imbalance between
in-phase branch and quadrature branch and there are also some disadvantages such as direct
current zero excursion and difficulty to debug. But these problems can be avoided by using all
digital Costas loop. The digital model can be derived such that the response of a digital Costas
loop follows that of the analog Costas loop and PLL. The digital design of the system is based on
direct transformation of every analog component of the Costas loop to its respective discrete time
and subsequent digital domain.
17. 3.1 General Description
Modulation is the process of varying Phase, Frequency or Amplitude of a sinusoidal carrier using
an information bearing signal. When the information signal is analog (audio) then, the
modulation is called Phase, Frequency or Amplitude Modulation respectively. Similarly, when
the information signal is digital (bits 1/0), the modulation is called Phase, Frequency or
Amplitude Shift Keying respectively.
Amplitude shift keying (ASK) which represents digital data as the variations in amplitude of the
carrier wave is not often used due to high noise susceptibility. Frequency shift keying (FSK), in
which a finite number of frequencies are utilized for representing the digital data, has been
predominantly used for uplink in Spacecraft Telecommand System due to the simplicity in
demodulator realization.
However, because of the better spectral efficiency, the new generation spacecrafts are currently
using Phase Shift Keying(PSK) even though the implementation complexity is higher than that
of ASK and FSK. Developed during the early days of the deep space programs, phase-shift
keying now finds widespread use in both military and commercial communication systems. For
18. telemetry applications, PSK is considered an efficient form of data modulation because it
provides the lowest probability of error for a given received signal level, when measured over
one symbol period. Terrestrial microwave radio links and satellite communication systems also
frequently employ PSK as their modulation format.
3.2 Phase Shift Keying
Phase-shift keying (PSK) is a modulation process whereby the input signal, a binary PCM
waveform, shifts the phase of the output waveform to one of a fixed number of states.
The signal can be written as in the equation,
Vo(t)= V 2S Sin [ωt+2pi(i-1)/M]
Where, I = 1, 2,... M
Vo = Output Voltage
ω = Carrier Frequency
S = the average signal power over the signaling interval (Ts),
M= (2^N) the number of allowable phase states 2p (i - 1).
3.3 PSK Demodulation
The demodulation process can be divided into three major sections. First, since the incoming
waveform is suppressed carrier in nature, coherent detection is required. The methods by which
a coherent carrier is derived from the incoming signal are termed, carrier recovery, and will be
covered first. Next, the raw data are obtained by coherent multiplication, and used to derive
clock-synchronization information. The raw data are then passed through the channel filter,
which shapes the pulse train so as to minimize intersymbol-interference distortion effects. The
19. shaped pulse train is then routed, along with the derived clock, to the data sampler which
outputs the demodulated data.
3.4 Carrier Recovery
Costas Loop is widely used for Carrier Recovery. It has the property of being able to derive a carrier
from the received signal, even when there is no component at carrier frequency present in that signal (eg:
DSBSC). The requirement is that the amplitude spectrum of the received signal be symmetrical about
this frequency.
The Costas loop is based on a pair of quadrature modulators - two multipliers fed with carriers in phase-
quadrature. These multipliers are in the in-phase (I) and quadrature phase (Q) arms of the arrangement.
Each of these multipliers is part of separate synchronous demodulators. The outputs of the modulators,
after filtering, are multiplied together in a third multiplier, and the low pass components in this product
are used to adjust the phase of the local carrier source - a VCO - with respect to the received signal.
The operation is to maximize the output of the ‘I’ arm, and minimize that from the ‘Q’ arm. The output
of the ‘I’ arm happens to be the message, and so the Costas loop not only acquires the carrier, but is a
(synchronous) demodulator as well.
21. As the design is new, a proof of concept model is initially developed in Simulink. This chapter
deals with the Simulink Model and its evaluation. The block diagram consists of the following
stages.
1. BPSK Modulator
2. Demodulator (Costas loop)
4.1 BPSK Modulator
Major Blocks present in the BPSK Modulator as shown in figure are as follows
• Bernoulli Binary generator
The Bernoulli Binary Generator block generates random binary numbers using a Bernoulli
distribution. The Bernoulli distribution with parameter p produces zero with probability p and
one with probability (1-p). The Bernoulli distribution has mean value (1-p) and variance p (1-p).
22. The Probability of a zero parameter specifies p, and can be any real number between zero and
one. This block is used to generate data. The random numbers here indicate the data to be
modulated.
• Unipolar to Bipolar generator
The output from the Bernoulli binary generator is obtained in the Unipolar form. To perform
conversion to Bipolar, this block is used. The Unipolar to Bipolar Converter block maps the
unipolar input signal to a bipolar output signal. If the input consists of integers between 0 and M-
1, where M is the M-ary number parameter, then the output consists of integers between -(M-1)
and M-1. The probability of occurrence of zero and one are equal (equal to 0.5) which is defined
in the parameter design list.
• VCO
The Continuous-Time VCO (voltage-controlled oscillator) block generates a signal with a
frequency shift from the quiescent frequency parameter that is proportional to the input signal.
The input signal is interpreted as a voltage.
• Product
The product performs BPSK modulation between the digital data and carrier signal.
4.2 Demodulator
It has the property of being able to derive a carrier from the received signal, even when there is
no component at carrier frequency present in that signal (e.g., DSBSC). The requirement is that
the amplitude spectrum of the received signal be symmetrical about this frequency. The Costas
loop is based on a pair of quadrature modulators – two multipliers fed with carriers in phase-
quadrature. These multipliers are in the in-phase (I) and quadrature phase (Q) arms of the
arrangement.
Each of these multipliers is part of separate synchronous demodulators. The outputs of the
modulators, after filtering, are multiplied together in a third multiplier, and the low pass
23. components in this product are used to adjust the phase of local carrier source – a VCO – with
respect to the received signal.
The 90 degree phase shift is brought out in the Q-arm by changing the phase parameter in the
design parameter list of the VCO connected to the Q-arm (labeled continuous time VCO1 in the
MATLAB simulink block diagram) The demodulation process can be divided into three major
subsections. First, since the incoming waveform is suppressed carrier in nature, coherent
detection is required. The methods by which a phase-coherent carrier is derived from the
incoming signal are termed, carrier recovery, and will be covered first. Next, the raw data are
obtained by coherent multiplication, and used to derive clock- synchronization information. The
raw data are then passed through the channel filter, which shapes the pulse train so as to
minimize inter symbol-interference distortion effects.
The filters used in the Costas loop are simple analog Chebyshev Type I low pass filters. The
input to this filter is sampled-based, continuous-time, real valued scalar signal. The magnitude
response of Chebyshev type I filter is equiripple in the passband and monotonic in the stopband.
Here, the filter order is 8, passband edge is 1rad/sec and passband ripple is 2dB. The output of
the I-arm from the Costas loop is given to the clock recovery logic.
25. 5.1 Overview
Libero IDE is the most comprehensive and powerful FPGA design and development software
available, providing start-to-finish design flow guidance and support for novice and experienced
users alike. Libero IDE combines Actel tools with such EDA powerhouses as Synplify,
ModelSim and ViewDraw.
Libero IDE software supports all Actel flash and antifuse products, including the popular IGLOO
FPGA, ProASIC3 FPGA, SmartFusion, Fusion FPGA, ProASICPLUS FPGA and Axcelerator
FPGA families.
26. 5.2 Features
Powerful project and design flow management
Full suite of integrated design entry tools and methodologies:
SmartDesign graphical SoC design creation with automatic abstraction to HDL
IP Core Catalog and configuration
User-defined block creation flow for design re-use
Synplify Pro ME synthesis fully optimizes Microsemi FPGA device performance and area
utilization
Synphony Model Compiler ME performs high-level synthesis optimizations within a
Simulink environment
Modelsim ME VHDL or Verilog behavioral, post-synthesis and post-layout simulation
capability
Physical design implementation, floorplanning, physical constraints, and layout
Timing-driven and power-driven place-and-route
SmartTime environment for timing constraint management and analysis
SmartPower provides comprehensive power analysis for actual and "what if" power
scenarios
Interface to FlashPro programmers
Post-route On Chip Debug Tools and Identify ME debugging software for Microsemi flash
designs
Silicon Explorer II debugging software for Microsemi antifuse designs
5.3 Synplify Pro ME
Synopsys Synplify Pro ME synthesis tool is integrated into Libero SoC and Libero IDE, enabling
you to target and fully optimize your HDL design for any Microsemi device. As with other
Libero tools, you can launch Synplify Pro ME directly from the Libero Project Manager.
27. Key features of Synplify Pro ME are listed below. All Microsemi devices are supported with
Synplify Pro ME.
Synopsys's Proprietary Behavior Extracting Synthesis Technology (BEST) Algorithms
Integrated Module Generation and Mapping
SCOPE Multi-Level Design Constraints
Language-Sensitive Editor
Intuitive Use Model with Intelligent Defaults
Direct Synthesis Technology
Third-Party Tool Integration
Advanced Register Detection
Hierarchy Browser Display
TCL Scripting
28. HDL Analyst Solution
Netlist Hierarchy
Comprehensive Mixed HDL Language Support
Multi-Point Synthesis
Retiming/register balancing
FSM Explorer
Graphical State Machine Viewer
Probe Point Creation
Generic Cross-Probing of Critical Paths
Gated Clock Conversion
Multiple Implementations
5.4 Model Sim ME
Mentor Graphics ModelSim ME HDL Simulator is a source-level verification tool, allowing you
to verify HDL code line by line. You can perform simulation at all levels: behavioral (pre-
synthesis), structural (post-synthesis), and back-annotated, dynamic simulation.
Coupled with the most popular HDL debugging capabilities in the industry, ModelSim ME is
known for delivering high performance, ease of use, and outstanding product support.
An easy-to-use graphical user interface enables you to quickly identify and debug problems,
aided by dynamically updated windows. For example, selecting a design region in the Structure
window automatically updates the Source, Signals, Process, and Variables windows. These cross
linked ModelSim windows create an easy-to-use debug environment. Once a problem is found,
you can edit, recompile, and re-simulate without leaving the simulator. ModelSim ME fully
supports current VHDL and Verilog language standards. You can simulate behavioral, RTL, and
gate-level code separately or simultaneously. ModelSim supports all Microsemi FPGA libraries,
ensuring accurate timing simulations.
The comprehensive user interface makes efficient use of desktop real estate. The intuitive
arrangement of interactive graphical elements (windows, toolbars, menus, etc.) makes it easy to
29. view and access the many powerful capabilities of ModelSim. The result is a feature-rich user
interface that is easy to use and quickly mastered.
5.5 FPGA Design Flow in Libero
The Libero Design Flow consists of six steps:
Step One - Design Creation
Plan out your design and enter it as HDL (VHDL or Verilog), structural schematic, or mixed-
mode (schematic and RTL).
30. Step Two - Design Verification - Functional Simulation
After you have defined your design, you must verify that it functions the way you intended. After
creating a testbench using WaveFormer Lite, use the ModelSim VHDL or Verilog simulator to
perform functional simulation on your schematic or HDL design.
Step Three - Synthesis/EDIF Generation
A design must be synthesized if the design was created using VHDL or Verilog. Use Synplify
AE or Synplify Pro from Synplicity to generate your EDIF netlist. You can re-verify your design
"post-synthesis" using the VHDL or Verilog ModelSim simulator used in step two.
31. While all RTL code must be synthesized, pure schematic designs are automatically "netlisted"
out via the Libero tools to create a structural VHDL or structural Verilog netlist.
Step Four - Design Implementation
After you have functionally verified that your design works, the next step is to implement the
design using the Actel Designer software. The Designer software automatically places and
routes the design and returns timing information. Use the tools that come with Designer to
further optimize your design. Use Timer to perform static timing analysis on your
design, ChipEditor or ChipPlannerto customize your I/O macro placement, PinEditor for I/O
customization, SmartPower for power analysis, and NetlistViewer to view your netlist.
Step Five - Timing Simulation
After you are done with design implementation, you can verify that your design meets timing
specifications. After creating a test bench using WaveFormer Lite, use the ModelSim VHDL or
Verilog simulator to perform timing simulation.
Step Six - Device Programming
Once you have completed your design, and you are satisfied with the timing simulation, create
your programming file. Depending upon your device family, you need to generate
a Fuse, Bitstream, or STAPL programming file.
33. 6.1 INTRODUCTION
Costas loop is a kind of closed loop auto tracking system that can be applied in tracking the input
signal’s phase. The Costas loop performs both phase coherent suppressed carrier reconstruction
and synchronous data detection within the loop. It is widely used in fields of radio technology
and has become an indispensable part of communication, radar, navigation, electronic equipment
and other devices. It performs a quadrature mix between a reference oscillator waveform and a
received waveform to form two error signals, which when multiplied together creates a suitable
signal for adjusting the Voltage Controlled Oscillator (VCO).
The basic block diagram of Costas loop is shown below, the input signals are sent to two
multipliers of the upper called in-phase branch and the lower called quadrature branch. The in-
phase branch multiplies input by VCOs output, the quadrature branch multiplies the input by
VCOs output after 90° phase shift. The multiplier outputs of the in-phase and quadrature
branches are passed through the low-pass filter, then multiplied together to get the error signal.
The error signal is filtered by the loop filter, whose output is the control voltage which controls
VCOs phase and frequency.
Let the input signal be a double sideband suppressed carrier is given by,
u(t) = s(t) cos ( ωct + θ )
And let the VCO outputs be,
v1(t) = k cos ( ωct + θ’ )
v2(t) = k sin ( ωct + θ’ )
The phase difference between the local carrier and the input carrier is ∆θ = ( θ’ – θ )
34. The output signal after the multiplication is,
v3(t) = s(t) cos ( ωct + θ ) * k cos ( ωct + θ’ )
= ½ ks(t) [ cos ∆θ + cos ( 2ωct + θ + θ’ ) ]
v4(t) = s(t) cos ( ωct + θ ) * k sin ( ωct + θ’ )
= ½ ks(t) [ sin ∆θ + sin ( 2ωct + θ + θ’ ) ]
The LPF output is given by,
v5(t) = ½ ks(t) cos ∆θ
v6(t) = ½ ks(t) sin ∆θ
The phase error signal is,
vd(t) = 1/8 ks2
(t) sin 2∆θ
vd controls the VCO through the Loop Filter. After several cycles, ∆θ changes very small, (sin
∆θ ≈ ∆θ), the phase error gradually is reduced to very small values finally. This time, v1(t) is the
synchronization carrier we need; v5(t) is the demodulator output signal. If there is a phase
difference, a non-zero control voltage will be generated and the frequency of the oscillator will
be adjusted accordingly. In the lock state the control voltage vanishes and the frequency of the
oscillator remains unchanged. The quadrature branch of the Costas loop thus tracks the
frequency and phase of the carrier while the in-phase of the Costas loop yields the baseband
signal.
The block diagram of digital Costas loop is shown below, in which all the analog modules are
replaced by digital modules. They are: Numerically Controlled Oscillator (NCO), Low-pass
Filter (LPF), Phase Detector (PD) and Loop Filter. Loop filter is used to adjust the phase error.
The adjusted phase error is used to control the NCO to generate the corresponding carrier
frequency.
35. When the carrier frequency generated by NCO coincides with the receiver carrier frequency, the
demodulated signal can be extracted from the in-phase branch. The implementation of Costas
loop using digital ICs increases the size of the circuit, where FPGA based implementation is
simple and the size is very compact. In FPGAs manual tuning is not required but in analog and
digital circuits manual tuning is required which is a time consuming process.
6.2 NUMERICALLY CONTROLLED OSCILLATOR
Numerically controlled oscillator (NCO) is a digital signal generator which creates a clocked,
discrete-valued representation of a waveform, usually sinusoidal. NCO is implemented using the
DDS approach. It consists of one phase accumulator and a ROM waveform table. The sine and
cosine signals were generated by using the method of look up table.
The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic
to synthesize a complete sine wave from one quadrature-cycle of data from the phase
accumulator. The phase-to-amplitude lookup table generates the remaining data by reading
forward then back through the lookup table. DDS offers fast switching between output
frequencies, fine frequency resolution and the digital architecture of DDS also eliminates the
need for manual tuning.
Numerically controlled oscillator is used instead of voltage controlled oscillator. The goal of
NCO is to produce two local orthogonal carrier signals. The direct frequency synthesizer
technology is adopted for that purpose. NCO consist of two parts, phase accumulator and ROM
waveform tables. Orthogonal signals are generated using method of lookup table. The output
36. frequency is defined as 0,
Where fs is sampling frequency, N is phase accumulator word size and ∆ is phase increment.
Here is the output of the phase detector, which is filtered by loop filter and gives discrete phase
increment value. Phase increment value ∆[ ] is given by,
Where, fc is the center frequency. The output of the phase accumulator [ ] is given by after
phase wrapping
Output of the NCO is written as,
So, after putting phase accumulator output in above equations, output of numerically controlled
oscillator is given by,
These sine and cosine waves are used for coherent demodulation of input signals.
6.3 ARM FILTER
The function of low pass filter is to remove 2ωc component from mixer outputs. For better
performance, two low pass filters with identical performance for in-phase and quadrature
branches are required. However it is not possible with the analog low pass filters. With the help
of digital implementation low pass filters with identical performance can be implemented. Finite
37. impulse response filters are used because of their linear phase characteristics. If order of low pass
filter is high, performance would be better but it consumes more hardware resource. Pass band
and stop band frequencies and attenuation should be selected according to performance tradeoffs.
General structure of a low pass FIR filter is shown below.
6.4 LOOP FILTER
Loop filter plays a key role in costas loop. Its main function is to filter out the high frequency
phase detector leakage component. This filter generates the VCO control voltage according to
the error from the multiplication. Usually the loop filter used is first order filter, but a first order
filter can track only phase differences. A second order system is able to track both phase and
frequency differences. The third-order loop can track phase, frequency and acceleration. These
loops are important when the transmitter or receiver is experiencing Doppler shifts. So, for
airborne and satellite based transmitters and receivers third-order PLL is used. The loop filter is
implemented as an IIR filter with the following design.
39. 7.1 Procedural Design
The figure above shows the design hierarchy of the complete system designed.
This is the post-synthesis look of the project flow on Libero.
41. 7.2 NCO
The above figure shows the RTL Schematic of NCO block design
7.3 Arm Filter
The above figure shows the RTL Schematic of Arm Filter block design
The vertical blocks are the multipliers and the horizontal ones are DFFs.
42. 7.4 Loop Filter
The above figure shows the RTL Schematic of Loop Filter block design
44. 8.1 Top Entity (Costas Loop)
begin
CLOCK_DIVIDER: clkdiv generic map(div=>2) port map(clk, reset, clk_out);
--NCO phase multiplier
N: nco port map(clk_out(0), reset, nco_input, nco_sin, nco_cos);
--Multiplier
M0: mult generic map(a_word_size=>nco_sin'length, b_word_size => carrier'length) port
map(nco_sin, carrier, mult_sin);
M1: mult generic map(a_word_size=>nco_sin'length, b_word_size => carrier'length) port
map(nco_cos, carrier, mult_cos);
--FIR Filter
L0: arm_filter port map(clk_out(0), reset, mult_sin, raw_op_sin);
L1: arm_filter port map(clk_out(0), reset, mult_cos, raw_op_cos);
--Extract output (Comparator)
COMPARATOR: op <= raw_op_cos(raw_op_cos'length -1); --Sign bit
--Error Multiplier
EM: mult generic map(a_word_size=>raw_op_sin'length, b_word_size =>
raw_op_cos'length) port map(raw_op_sin, raw_op_cos, mult_error_op);
--Loop Filter
--NCO mapping to error
LF: loop_filter port map(clk_out(1), reset, mult_error_op, f_desired, nco_input);
end arch;
8.2 Arm Filter
begin
GEN_DFF_SHIFT: for i in 0 to taps generate
x_inPUT: if i = 0 generate
T0:dff
generic map(word_size => x_in'length)
45. port map(clk, reset, x_in, (others => '0'), words(i));
end generate x_inPUT;
SHIFT_REGS: if i > 0 generate
TX: dff
generic map(word_size => x_in'length)
port map(clk, reset, words(i-1),(others => '0'), words(i));
end generate SHIFT_REGS;
end generate GEN_DFF_SHIFT;
GEN_MULT: for i in 0 to taps generate
MX: mult
generic map(a_word_size=> x_in'length, b_word_size=>coeff_length)
port map(words(i), coeffs(i), mult_words(i));
end generate GEN_MULT;
GEN_SUM: for i in 0 to taps generate
SUM_0: if i = 0 generate
S0: sum_words(0) <= mult_words(0);
end generate SUM_0;
SUM_ELSE: if i > 0 generate
SX: sum_words(i) <= sum_words(i-1) + mult_words(i);
end generate SUM_ELSE;
end generate GEN_SUM;
GEN_Y: y_out <= sum_words(sum_words'length -1);
end arch;
47. 8.4 NCO
begin
-- link signal to MSBs of variable
R0: pa generic map(fword_width=>fword_width, accsum_width=> accsum_width)
port map(clk, reset, fword, connector);
R1: pac port map(connector, op_sin);
phase_shifted_connector <= connector + phase_shift;
R2: pac port map(phase_shifted_connector, op_cos);
end arch;
49. A Costas Loop for BPSK detection was successfully. The first and foremost requirement of this
design was to generate or recover a carrier frequency at the receiver and then matching that with
the phase/frequency of the incoming BPSK signal. This was achieved with the help of a NCO in
configuration for this demodulator design. In this design a first order loop filter was scaled to an
incoming data rate. Filters need to be optimized such that their bandwidth is wide enough to
minimize ISI and narrow enough to minimize noise. This Costas loop can see incoming signal
phases of 0˚ and 180˚ and demodulate the data stream up to 50Mbps. The Costas BPSK Detector
consumes 144mw of power.
The design can be implemented with higher order loop filter for better response with the trade-
off on chip area and cost. A coherent BPSK demodulator using anti-parallel synchronization loop
could be implemented which uses differential NCO instead of a quadrature NCO. This will
considerably reduce the chip area and improve the performance. Spacecraft Telecommand
Systems have adopted Phase Shift Keying (PSK) for the advantages it provides over the other
types of modulations such as Amplitude Shift Keying (ASK) and Frequency Shift Keying (FSK).
As per the specifications for Telecommand Subcarrier Modulation, the carrier is always an
integral multiple of bit rate. This can be the motivation to further develop a clock recovery
scheme which can use the already recovered carrier from demodulation process and simplify the
clock recovery process. Incidentally, in the existing design of Digital PSK demodulators, the
carrier and clock recovery functions are implemented as two independent entities with only the
demodulated data signal being passed from carrier recovery to clock recovery function.
Since the carrier and clock are independently recovered, the time to acquire receiver
synchronization is on the higher side. Taking the advantage of the above mentioned feature in
telecommand subcarrier modulation specification, the carrier recovered is extended to clock
recovery in order to reduce the time for synchronization compared to the existing PSK
demodulator.
50. REFERENCES
[1] Costas, John P. (1956). "Synchronous communications". Proceedings of the IRE 44 (12):
1713–1718. doi:10.1109/jrproc.1956.275063.
[2] Shida, S., Fushimi, S. and Tsuchiya, T. (1984). “FIR Low-Pass Filter Design Using
Parametric Filter Technique”. IEEE transactions on circuits and systems, vol. cas-31, no. 5.
[3] Taylor, D. (2002). “Introduction to ‘Synchronous Communications’, A Classic Paper by John
P. Costas”. Proceedings of the IEEE 90 (8): 1459–1460. doi:10.1109/jproc.2002.800719.
[4] Feigin, J. (2002). "Practical Costas loop design". RF Design: 20–36.
[5] Popek, G. and Kampik, M. (2009). “Low-Spur Numerically Controlled Oscillator Using
Taylor Series Approximation”. XI International PhD Workshop OWD 2009.
[6] Guo, L., OuYang, M. and Cai, J. (2011). “Simulation and Implementation of Costas Loop
Based on FPGA”. IEEE 978-1-4244-8039-5/11.
[7] Shamla, B and Gayathri Devi, K.G. (2012). “Design and Implementation of Costas loop for
BPSK Demodulator”. IEEE 978-1-4673-2272-0/12.
[8] Roshna, T. R., Nivin, R., Sherly, J., Apren, T. J. and Alex, V. (2013). “Design and
Implementation of Digital Costas Loop and Bit Synchronizer in FPGA for BPSK
Demodulation”. IEEE 978-1-4799-0575-1/13.
[9] Cui Guo-wei and Wang Feng-ying. (2013). “The Implementation of FIR Low-pass Filter
Based on FPGA and DA”. IEEE 978-1-4673-6249-8/13.
[10] Dangui, Y., Ruijun, T., Min, X. and Chengchang, Z. (2014). “An optimal method for Costas
Loop design based on FPGA”. IEEE 978-0-7695-5016-9/13.
[11] Pujari, S.S., Muduli, P.P., Panda, A., Badhai, R., Nayak, S. and Sahoo, Y. (2014). “Design
& Implementation of FIR Filters using On-Board ADC-DAC & FPGA”. IEEE ISBN
No.978-1-4799-3834-6/14.
51. APPENDICES
A1 Implementation on a FPGA Board
A1.1 Field Programmable Gate Arrays
At the highest level, FPGAs are reprogrammable silicon chips. Using prebuilt logic blocks and
programmable routing resources, user can configure these chips to implement custom hardware
functionality without ever having to pick up a breadboard or soldering iron. The user develops
digital computing tasks in software and compiles them down to a configuration file or bit stream
that contains information on how the components should be wired together. In addition, FPGAs
are completely reconfigurable and instantly take on a brand new “personality” when recompiled
a different configuration of circuitry. In the past, FPGA technology could be used only by
engineers with a deep understanding of digital hardware design. The rise of high-level design
tools, however, is changing the rules of FPGA programming, with new technologies that convert
graphical block diagrams or even C code into digital hardware circuitry.
FPGA chip adoption across all industries is driven by the fact that FPGAs combine the best parts
of ASICs and processor-based systems. FPGAs provide hardware-timed speed and reliability,
but they do not require high volumes to justify the large upfront expense of custom ASIC design.
Reprogrammable silicon also has the same flexibility of software running on a processor-based
system, but it is not limited by the number of processing cores available. Unlike processors,
FPGAs are truly parallel in nature, so different processing operations do not have to compete for
the same resources. Each independent processing task is assigned to a dedicated section of the
chip, and can function autonomously without any influence from other logic blocks. As a result,
the performance of one part of the application is not affected when added more processing.
A1.2 Benefits of FPGA Technology
• Performance
• Time to Market
• Cost
52. • Reliability
• Long-Term Maintenance
• Performance—Taking advantage of hardware parallelism, FPGAs exceed the computing power
of digital signal processors (DSPs) by breaking the paradigm of sequential execution and
accomplishing more per clock cycle. BDTI, a noted analyst and benchmarking firm, released
benchmarks showing how FPGAs can deliver many times the processing power per dollar of a
DSP solution in some applications. Controlling inputs and outputs (I/O) at the hardware level
provides faster response times and specialized functionality to closely match application
requirements.
• Time to market—FPGA technology offers flexibility and rapid prototyping capabilities in the
face of increased time-to-market concerns. An idea or concept can be first put to test and verify it
in hardware without going through the long fabrication process of custom ASIC design. Then
implement incremental changes and iterate on an FPGA design within hours instead of weeks.
Commercial off-the-shelf (COTS) hardware is also available with different types of I/O already
connected to a user-programmable FPGA chip. The growing availability of high-level software
tools decreases the learning curve with layers of abstraction and often offers valuable IP cores
(prebuilt functions) for advanced control and signal processing.
• Cost—The nonrecurring engineering (NRE) expense of custom ASIC design far exceeds that of
FPGA-based hardware solutions. The large initial investment in ASICs is easy to justify for
OEMs shipping thousands of chips per year, but many end users need custom hardware
functionality for the tens to hundreds of systems in development. The very nature of
programmable silicon means you have no fabrication costs or long lead times for assembly.
Because system requirements often change over time, the cost of making incremental changes to
FPGA designs is negligible when compared to the large expense of re-spinning an ASIC.
• Reliability—Although software tools provide the programming environment, FPGA circuitry is
truly a “hard” implementation of program execution. Processor-based systems often involve
several layers of abstraction to help schedule tasks and share resources among multiple
processes. The driver layer controls hardware resources and the OS manages memory and
processor bandwidth. For any given processor core, only one instruction can execute at a time,
and processor-based systems are continually at risk of time critical tasks preempting one another.
53. FPGAs, which do not use OSs, minimize reliability concerns with true parallel execution and
deterministic hardware dedicated to every task.
• Long-term maintenance—As mentioned earlier, FPGA chips are field-upgradable and do not
require the time and expense involved with ASIC redesign. Digital communication protocols, for
example, have specifications that can change over time, and ASIC-based interfaces may cause
maintenance and forward-compatibility challenges. Being reconfigurable, FPGA chips can keep
up with future modifications that might be necessary. As a product or system matures, you can
make functional enhancements without spending time redesigning hardware or modifying the
board layout.
54. A2 Glossary
ASK Amplitude Shift Keying
AWGN Additive White Gaussian Noise
BPSK Binary Phase Shift Keying
CSG Communication Systems Group
DDS Direct Digital Synthesis
DSG Digital Systems Group
DSP Digital Signal Processing
DUT Device Under Test
FPGA Field Programmable Gate Array
HDL Hardware Description Language
LFSR Linear-Feedback Shift Register
MATLAB Matrix Laboratory
FSK Frequency Shift Keying
IDE Integrated Design Environment
PSK Phase Shift Keying
RTL Register Transfer Logic
TC Telecommand
TCD Telecommand Division
VHDL VHSIC Hardware Description Language
