1. Space Qualified Drive, Sense and Control
Electronics for Mirror Positioning System
by
Christopher M Parmar
(140010741003)
Guided By:
Dr. Viranchi C Pandya
Associate Professor, ADIT
Co-Guide :
Mr. Mohammad Waris
Scientist Engineer (SE)
Space Applications Center, ISRO
A Thesis Submitted to
Gujarat Technological University
in Partial Fulfillment of the Requirements for
the Degree of Master of Engineering
in Signal Processing & Communication
May, 2016
Electronics & Communication Department
A D Patel Institute of Technology
New Vallabh Vidyanagar, Anand (388121)
2. Certificate
This is to certify that research work embodied in this thesis entitled “Drive,
Sense and Control Electronics for Mirror Positioning System” was
carried out by Christopher M Parmar (Enrollment no. 140010741003)
studying at A. D. Patel Institute of Technology (001) for fulfillment of
Master of Engineering degree to be awarded by Gujarat Technological University.
He has complied to the comments given by the Dissertation Phase-I as well as Mid
Semester Thesis Reviewer to my satisfaction.
Guide
Dr. Viranchi C. Pandya
Electronics and Communication
Engineering Deparment
A. D. Patel Institute of Technology
Principal
Dr. R. K. Jain
A. D. Patel Institute of Technology
Seal of the Institute
Date : 20th
May, 2016
Place : A. D. Patel Institute of Technology, New V V Nagar.
I
3. Industry Certificate
This is to certify that research work embodied in this thesis entitled “Drive,
Sense and Control Electronics for Mirror Positioning System” was
carried out by Christopher M Parmar (Enrollment no. 140010741003)
studying at A. D. Patel Institute of Technology (001) for fulfillment of
Master of Engineering degree to be awarded by Gujarat Technological University.
He has complied to the comments given by the Dissertation Phase-I as well as Mid
Semester Thesis Reviewer to my satisfaction.
Industry Guide
Mohammad Waris
Scientist Engineer(SE)
Space Applications Center, ISRO
Jodhpur Tekra, Ahmedabad
Head of the Department
Sri. Sanjeev Mehta
Sensor Front-End Electronics
Development Division (SFED),
Sensor Electronics Group (SEG),
Space Applications Center (SAC), ISRO
Jodhpur Tekra, Ahmedabad
Date : 20th
May, 2016
Place : Space Applications Center, ISRO, Jodhpur Tekra, Ahmedabad.
II
4. Compliance Certificate
This is to certify that research work embodied in this thesis entitled “Drive,
Sense and Control Electronics for Mirror Positioning System” was
carried out by Christopher M Parmar (Enrollment no. 140010741003)
studying at A. D. Patel Institute of Technology (001) for fulfillment of
Master of Engineering degree to be awarded by Gujarat Technological University.
He has complied to the comments given by the Dissertation Phase-I as well as Mid
Semester Thesis Reviewer to my satisfaction.
Candidate Name
Christopher M Parmar
Enroll. No: 140010741003
Electronics and Communication
Engineering Deparment
A. D. Patel Institute of Technology
Guide
Dr. V. C. Pandya
Electronics and Communication
Engineering Department
A. D. Patel Institute of Technology
Industry Guide
Mohammad Waris
Scientist Engineer(SE)
Space Applications Center, ISRO
Jodhpur Tekra, Ahmedabad
Date : 20th
May, 2016
Place : A. D. Patel Institute of Technology, New V V Nagar.
III
5. Paper Publication Certificate
This is to certify that research work embodied in this thesis entitled “Drive,
Sense and Control Electronics for Mirror Positioning System” was
carried out by Christopher M Parmar (Enrollment no. 140010741003)
studying at A. D. Patel Institute of Technology (001) for partial fulfill-
ment of Master of Engineering degree to be awarded by Gujarat Technological
University has published article “Design of high voltage full bridge driver
for piezoelectric actuator for space applications” for publication by the 5th
International Conference on Power Systems (ICPS’2016) at Indian In-
stitute of Technology, New Delhi) during on 4th
to 6th
March, 2016.
Date: 20th
May, 2016
Place: A. D. Patel Institute of Technology
Candidate Name
Christopher Parmar
(140010741003)
Guide
Dr. Viranchi C. Pandya
Electronics and Communication
Engineering Deparment
A. D. Patel Institute of Technology
Principal
Dr. R. K. Jain
Seal of the Institute
IV
6. Thesis Approval Certificate
This is to certify that research work embodied in this thesis entitled “Drive,
Sense and Control Electronics for Mirror Positioning System” was
carried out by Christopher M Parmar (Enrollment no. 140010741003)
studying at A. D. Patel Institute of Technology (001) for partial fulfillment
of Master of Engineering with specialization if Signal Processing & Communica-
tion by Gujarat Technological University.
Date:
Place:
Examiner’s Name & Sign
( ) ( )
V
7. Undertaking About Originality of
Work
We hereby certify that we are the sole authors of this thesis and that neither
any part of this thesis nor the whole of the thesis has been submitted for a degree
to any other University or Institution.
We certify that, to the best of our knowledge, the current thesis does not in-
fringe upon anyone’s copyright nor violate any proprietary rights and that any
ideas, techniques, quotations or any other material from the work of other people
included in our thesis, published or otherwise, are fully acknowledged in accor-
dance with the standard referencing practices. Furthermore, to the extent that
we have included copyrighted material that surpasses the boundary of fair dealing
within the meaning of the Indian Copyright (Amendment) Act 2012, we certify
that we have obtained a written permission from the copyright owner(s) to include
such material(s) in the current thesis and have included copies of such copyright
clearances to our appendix.
We declare that this is a true copy of thesis, including any final revisions, as
approved by thesis review committee.
We have checked write up of the present thesis using anti-plagiarism database
and it is in allowable limit. Even though later on in case of any complaint per-
taining of plagiarism, we are sole responsible for the same and we understand
that as per UGC norms, University can even revoke Master of Engineering degree
conferred to the student submitting this thesis.
Date: 20th
May, 2016
Signature of Student:
Name of Student:Christopher Parmar
Enrollment No: 140010741003
Signature of Guide:
Name of Guide: Dr. V C Pandya
Institute Code: 001
VI
8. Acknowledgement
I gratefully express my sincere gratitude to my guide Dr. Viranchi C Pandya
for his invaluable guidance, constant encouragement and support throughout this
work. I am also very much thankful for my industry guide Mr. Mohammad
Waris, Scientist(SE), Space Application Center, Indian Space Research Organiza-
tion, for his invaluable motivation, guidance and support. I also thank Sri. Sanjeev
Mehta, Head of Department, SFED/SEG/SEDA and Sri. Arup Roy Chowdhury,
Group Head, SEG/SEDA for their support throughout dissertation. I personally
thank Sri. Manish Mehta and Sunil Bhati for their continuous motivation and sup-
port throughout my hardware testing work. Without their constant effort, this
work would never be completed. I am also thankful to all working scientists and
lab members of SFED/SEG/SEDA, SAC, ISRO for their help and encouragement
throughout the dissertation.
I am sincerely thankful to Dr. V K Thakar (HOD) for providing me important
suggestions to perk up this project. His support during the final phase of my
project was very influential. I am also very thankful to all lab assistance of A D
Patel Institute of Technology for their constant support.
I am so much thankful to all my classmate of 2013 batch at A D Patel Institute
of Technology and all my friends at ISRO, for their constant help and support.
Non of these could be done without their love, friendship and cheerfulness during
course of my dissertation.
Lastly, I would like to thank my family for offering me constant inspiration and
sustenance during the different stages of the task.
Christopher Parmar
(140010741003)
VII
9. Date : 20th
May, 2016
Place : A. D. Patel Institute of Technology, New V V Nagar.
VIII
17. Abstract
Camera and its electronics are one of the major parts in space crafts payloads.
To focus high resolution image, the position of mirror is very crucial and must be
finely calibrated . Due to several circumstances like external forces surrounding the
satellite, the position of the mirror can be deviated from its original position. This
deviation can be in nanometer to micrometer, but this minor change can disturb
the focusing of the camera of satellite. To control this position of mirror, control
electronics is required to continuously monitor the current position of the camera
and if deviation is found, it can recalibrate the original position. The purpose of
this dissertation is to design a high efficiency drive , sense and control electron-
ics using actuator to minimize error of mirror positions of satellite camera. The
piezoelectric actuator is used for micro-positioning of mirror of telescope. The re-
port discusses about modeling of piezoelectric actuator, its driving techniques and
full system design of mirror positioning using piezoelectric actuator with feedback
sensing mechanism. Two stage design is presented which uses switching amplifier.
First stage is dc-dc flyback converter and second stage is high voltage full bridge
driver. Both the stages are modeled, designed and simulated in OrCad Capture
PSpice software to get optimal performance. The obtained efficiency of dc-dc fly-
back converter is 71.88% and full bridge converter is 89.6%. Laboratory prototype
of reduced scale full bridge converter is developed and PCB is fabricated for testing
purpose. The switching frequency of full bridge amplifier is 10KHz. PWM was
generated using FPGA kit. The analysis includes different current and voltage
waveform measurements . The achieved efficiency of prototype hardware is 66.93
%.
18. CHAPTER 1
Introduction
1.1 Industry Profile
1.1.1 Location
Figure 1.1: Space Applications Center, ISRO, Ahmedabad
Space Application Center- Indian Space Research Organization is located at Jodh-
pur Tekra, near Ambavadi vistar, Satellite, Ahmedabad, Gujarat. It is approx-
imately 2 Kms from Iscon Cross road. It is 12 Kms from Ahmedabad Railway
Station. Two well-known landmarks near to the Organization are The Courtyard
Mariot Hotel and SPIPA.
1.1.2 History
The Indian Space Research Organization (ISRO) is the primary space agency of
India. ISRO is among the largest government space agencies in the world. Its pri-
mary objective is to advance space technology and use its applications for national
1
19. Christopher M Parmar 1.2. INTRODUCTION
benefit. Established in 1969, ISRO superseded the erstwhile Indian National Com-
mittee for Space Research (INCOSPAR), thus institutionalizing space activities
in India, which emanated from a shared vision of Jawaharlal Nehru and Vikram
Sarabhai, the 1st chairman of INCOSPAR.
ISRO built India’s first satellite, Aryabhata, which was launched by the Soviet
Union on 19 April in 1975. In 1980, Rohini became the first satellite to be placed
in orbit by an Indian-made launch vehicle, SLV-3. ISRO subsequently developed
two other rockets: the Polar Satellite Launch Vehicle (PSLV) for launching satel-
lites into polar orbits and the Geosynchronous Satellite Launch Vehicle (GSLV)
for placing satellites into geostationary orbits. These rockets have launched nu-
merous communications satellites and earth observation satellites. Satellite nav-
igation systems like GAGAN and IRNSS have been deployed. In January 2014,
ISRO successfully used an indigenous cryogenic engine in a GSLV-D5 launch of
the GSAT-14.
On 22 October 2008, ISRO sent its first mission to the Moon, Chandrayaan-1.
On 5 November 2013, ISRO launched its Mars Orbiter Mission, which successfully
entered the Mars orbit on 24 September 2014, making India the first nation to
succeed on its maiden attempt, and ISRO the first Asian space agency to reach
Mars orbit. Future plans include development of GSLV Mk III (for launch of
heavier satellites), development of a reusable launch vehicle, human spaceflight,
further lunar exploration, interplanetary probes, a satellite to study the Sun, etc.
Over the years, ISRO has also conducted a variety of operations for both Indian
and foreign clients. ISRO has several field installations as assets, and cooperates
with the international community as a part of several bilateral and multilateral
agreements. In June 2014, it launched five foreign satellites by the PSLV. There
are plans for the development and launch of a satellite which will be collectively
used by the eight SAARC nations.
1.2 Introduction
For space crafts, the demand of smart and efficient actuation techniques is increas-
ing because more complex instruments and robotic mechanisms are implemented
in satellite. In space vehicles, actuators produces useful motion for performing
Gujarat Technological University, Ahmedabad 2
20. Christopher M Parmar 1.2. INTRODUCTION
actions such as:
1. Engaging , disengaging or separating space craft vehicles
2. Micro-positioning of mirrors of camera
3. Opening and closeting of covers, shield and solar array driving system in
space
4. Deploying, positioning, and retracting sensors, actuators, antennas and in-
struments
There are several methods available for actuation such as electromagnetic ,elec-
trostatic, thermomechanical, phase change, piezoelectric,shape memory, magne-
tostrictive, electrohelogical, electrohydrodynemaic and diamagnetism. Thermo-
mechanical, phase change and piezoelectric actuation methods are very good in
terms of efficiency, speed and power density. While all the technologies described
above have been studied and tested in the laboratory, not all have been applied yet
in commercial products or spacecraft components. All-electric air-craft concept is
widely employed nowadays. It has many advantages such as :
ˆ Increased safety due to elimination of poisonous and flammable hydraulic
fluids
ˆ Easier and reduced maintenance due to elimination of hydraulic leaks and
better diagnostability
ˆ Reduced weight and complexity of power transmission paths
ˆ Better energy efficiency of electrically powered systems
ˆ Better actuator dynamics (esp. Flow control of helicopter applications)
The electromagnetic, hydraulic and pneumatic actuators achieve displacement
indirectly by moving a piston by electromagnetic force or pressure. On the other
hand, the piezoelectric actuator achieves displacement by directly applying de-
formation of a solid, and thus gives a higher displacement accuracy, higher force
generation, higher response speed , high power density and extremely low steady
state power consumption than other types of actuator. To meet the space applica-
tion needs, actuator has to comply with factors such as higher reliability, operation
Gujarat Technological University, Ahmedabad 3
21. Christopher M Parmar 1.3. MOTIVATION
in harsh environment such as vacuum and heavy radiation. Large research is hap-
pening in the domain of modeling of actuator, designing of driving techniques and
system optimization.
1.3 Motivation
Mirror positioning is an important mechanism which is used to correct the posi-
tional error of a mirror in camera of satellite. Due to environmental factor outside
the satellite, the position of the camera mirror can be disturbed. The position
error may vary from nanometer to micrometer.The actuator which is used to cor-
rect this position error should have very fine resolution in terms of nanometer to
micrometer. The functional block diagram of the required system is shown in fig-
ure Figure 1.2. On detection of the positional error of the mirror on the satellite,
the positional command is given to the controller onboard, the controller decode
the command and gives control signal to driver circuit to actuate the actuator.
The design of driver electronics is based on the actuator type selected. The me-
chanical resolution, power consumption, thrust force generated by the actuator,
drive voltage/current and durability are the major selection criteria when we com-
pare different types of actuators.
ˆ Stepper motor based Actuator
ˆ Piezoelectric driven Actuator
ˆ Thermal heaters
ˆ Magnetic actuator
Magnetic actuator and thermal actuator consumes very high dc current which re-
sults in high power losses. The stepper motor based actuators takes pulsed current
but generated thrust force is lower than piezoactuator. Piezoelectric actuator fits
in this criteria. It gives very high resolution in terms of nanometer. The power
consumption is very low as it takes pulsed current (in mA), as well as the gener-
ated thrust force is very high compared to all other actuators. But the driving
voltage of the piezoactuator is very high (in terms of hundreds or thousands of
volts) which makes design of driving electronics a challenging task.
Gujarat Technological University, Ahmedabad 4
22. Christopher M Parmar 1.4. SCOPE OF THE THESIS
Figure 1.2: Functional Block Diagram
Figure 1.3: Proposed Piezoelectric actuator(Courtesy of Cedrat-technology)
1.4 Scope of the Thesis
According to the survey of different actuators, the best suited actuator is piezoelec-
tric actuator which satisfies all requirements for space environment. The objective
of the proposed thesis can thus be enumerated as follows :
1. To evaluate electrical behaviour of piezoelectric actuator and study differ-
ent possible driving techniques. The chosen driving technique should allow
higher efficiency and high durability.
2. To model, design and simulate chosen driver topology for piezoelectric ac-
tuator considering space environment. Components used for the simulation
and power calculations must be space grade components.
Gujarat Technological University, Ahmedabad 5
23. Christopher M Parmar 1.5. ORGANIZATION OF THE THESIS
3. To develop laboratory prototype PCB of driver circuit. This driver must be
tested for the actual power requirements of piezoelectric actuator.
1.5 Organization of the Thesis
Chapter 2 includes introduction of piezoelectric actuator and its applications.
It also includes literature survey of driving amplifiers for piezoelectric actuator.
Chapter 3 discusses basics of power converter and working of some of the basic
converter topologies. Chapter 4 includes modeling, design and simulation results
of second stage of driver circuit which is high voltage full bridge driver. Chapter
5 includes modeling, design and simulation results of first stage of driver circuit
which is dc-dc flyback converter. Chapter 6 includes Digitally Controlled PWM
generation using FPGA. Chapter 7 discusses development of laboratory prototype
of reduced scale H-Bridge driver circuit and its measurement results. Chapter 8
includes conclusion and future work.
Gujarat Technological University, Ahmedabad 6
24. CHAPTER 2
Literature Review
2.1 Piezoelectric Actuators and its Applications
Actuator applications of piezoelectric started in late 1970s till now aiming at con-
sumer applications such as precision positioners with high strain materials, mul-
tilayered device designing, and mass-fabrication processes for portable electronic
gadgets, robotics and smart mechanical structures. Because of the significantly
high energy efficiency of piezoelectric in examination with different actuators, for
example, synthetic motors and electromagnetic segments, piezo- electric actuators
have been regained its attention in this era to create the sustainable society[1]
.
There are basically three types of actuators such as stake type actuators, Exter-
nal/Internal leveraged actuators (such as linear and amplified PEA) and Frequency
leveraged actuators (such as stepping motors ad ultrasonic motors). They offer the
advantage of large deformation and large strokes. Because of a prestress applied
to the piezo ceramics and design of an efficient mechanical amplifier of piezoac-
tuator, it can produce large strokes both in static as well as dynamic conditions.
For these reasons, these actuators can be used for many industrial application,
robotics, optics and space applications for micro positioning, structure shaping,
structure active damping, generation of vibration, energy harvesting[2]
.
2.2 Drive techniques for piezoelectric actuators
2.2.1 Electrical Behaviour of Piezoelectric Actuator
Piezoelectric actuators can be classified into main three categories[2,3]
:
7
25. Christopher M Parmar 2.2. DRIVE TECHNIQUES FOR PIEZOELECTRIC ACTUATORS
1. Stake type actuators
2. External/Internal leveraged actuators (such as linear and amplified PEA)
3. Frequency leveraged actuators(such as stepping motors ad ultrasonic motors)
To design driving circuit of a PEA, efficient electrical modelling of PEA is nec-
essary. The electrical behaviour of a piezoelectric actuator is equivalent to a
capacitor with nonlinear capacitance. Large number of models are developed
which represents PEA behaviour electrically and mathematically starting with
Van Dyke model[4]
. They are generally classified as macroscopic and microscopic
models. Macroscopic models considers piezoactuator as whole where as micro-
scopic models considers piezoactuator as a combination of series of ferromagnetic
domains or discretized cells[5,6,7,8]
. Figure 2.1 is most basic model for PEA which
is used for the simulation of the driver in this paper. The Van Dyke Model is a
parallel connection of a series RLC which represents mechanical damping, mass,
and elastic compliance, and a capacitor represents the electrostatic capacitance
between the two parallel plates of the piezo-ceramic patch[9]
.
Figure 2.1: “Van Dyke” model of PEA[4]
2.2.2 Review of Drive Amplifiers for Piezoelectric Actua-
tor
As piezoelectric actuator is highly capacitive load, it requires very high driving
voltage and high driving current when operated at high frequency. For example,
stimulating voltage for Amplified piezoelectric actuator is several hundred volts
and for high voltage PEA it goes to several thousands volts.So the driving am-
plifier must withstand high current as well as high voltage. Figure 2.2 shows the
functional block diagram of typical PEA driver system. Normally, onboard power
supply varies from 28V to 42V for satellite. So DC-DC boost converter is required
Gujarat Technological University, Ahmedabad 8
26. Christopher M Parmar 2.2. DRIVE TECHNIQUES FOR PIEZOELECTRIC ACTUATORS
to boost this lower voltage to higher level. This high voltage biasing is given to
driver amplifier. The displacement of the PEA is controlled using control signal
which is given through controller. Low pass filter is a typical RC, LC or LLCC[10]
filter which reduces the ripple and noise in output voltage. By using feedback con-
trol mechanism, the displacement error in the actuation is sensed and corrected.
There are other number of compensator methods by which the nonlinearities of
PEA like hysteresis and creep is compensated[11]
.
Figure 2.2: Functional Block Diagram
Three types of amplifiers are developed for drive PEA, (1) Linear amplifier
(2) Switching amplifier and (3) Hybrid amplifier[12]
. Researchers have developed
linear amplifiers such as class A, class B or class AB amplifiers[13]
. An improved
class A amplifier is proposed in[14]
. Linear amplifiers have several advantages such
as low signal distortion, good static performance, high integration level, simple
structure and low electromagnetic interference[15]
. But it suffers from very low
efficiency and high energy dissipation. The Maximum ratio of stored energy to
dissipated energy is 50%, it means highest achievable efficiency is 33%[16]
. So it is
not commonly employed to drive Piezoelectric actuator.
Switch mode amplifiers are very good alternative in terms of efficiency, size and
weight. Variety of switch mode amplifier topologies have been developed such as
buck, buck-boost, half-bridge, full-bridge and flyback to actuate PEA. As Piezo-
electric actuator need only several hundred volts which can be easily achievable
using commercial amplifier, main focus of this paper is output driving stage. Drive
stage of PEA amplifies the voltage according to control signal given through con-
troller. Authors in[17,18,19,20]
also presented bidirectional buck-boost and bidirec-
Gujarat Technological University, Ahmedabad 9
27. Christopher M Parmar 2.2. DRIVE TECHNIQUES FOR PIEZOELECTRIC ACTUATORS
tional flyback topologies for driving capacitive actuators. The literature survey
dictates that most common topologies used for driving stages are bidirectional
buck[21,22,23,24]
and full bridge[10,25,26]
. The main focus of this paper is to design
full bridge driver circuit for PEA.
Gujarat Technological University, Ahmedabad 10
28. CHAPTER 3
An Overview of Switch Mode
Power converters
3.1 Introduction
In recent years, the field of power electronics has grown widely and penetrated in
every electronics devices. One can use linear amplifier or switch mode amplifier
to meet the power requirements of the systems. Linear amplifiers are good for low
powered devices. They are very popular because of their simplicity and ease of
use. However , they are not efficient due to the way they work. A linear amplifier
, the transistor operates in their active region. It dissipates the difference of input
and output voltage as heat. If the difference between output voltage and input
voltage is higher then heat generation will also be higher. In most cases, a linear
amplifier/regulator wastes more power in stepping down the voltage then to actu-
ally delivering to the target device. The linear amplifier has typical efficiency of
30-40 %, reaching as low as 14 %, which generates lots of heat and requires bulky
and expensive heat sinks to dissipate this heat.
On the other hand, the switching amplifier works by taking small amount of energy
from the input source, bit by bit, and delivers to the output load. This phenomena
is accomplished by electrical switching and a controller which regulates the rate
at which the energy is transferred. The energy lost in this phenomena is relatively
very small compared to linear amplifier. In switch mode power conversion process,
the transistor operates as a switch, fully ON and fully OFF, hence the power loss
reduces as compared to previous one. So efficiency of switch mode amplifier is
typically 85 %. Of course, there will be some energy loss when transistor switches
11
29. Christopher M Parmar 3.2. DESIRABLE CHARACTERISTICS OF POWER SWITCHES
from one state to another through active region. The power losses due to switching
increases with increase in switching frequency. The harmonic content of the out-
put consist of multiples of switching frequency fs. Suitable filters can be included
to reduce these harmonic components to acceptable levels. Optimum switching
frequency can be chosen to provide an acceptable trade-off between switching loss
and size and cost of the transformer and filter components. Due to advancements
in semiconductor technologies, controllable power switches are available now with
higher switching rates , so the switching frequency can be increased and filter
component and transformer size can be reduced.
3.2 Desirable Characteristics of Power Switches
There are several types of controllable switches such as bipolar junction tran-
sistor (BJT), metal oxide semiconductor field effect transistor (MOSFET), gate
turn off device (GTO), and insulated gate bipolar transistor (IGBT). The ideal
characteristics of these devices are as follows :
1. In on state, it can conduct arbitrarily large current with zero voltage drop.
2. In off state, it can block arbitrarily large forward and reverse voltage with
zero current flow.
3. During switching, it must be completely turn on or off instantaneously so
that it can be operated at high frequency.
4. Very small power required to control the switch. This will simplify the
control circuit.
5. Positive temperature coefficient of on-state resistance. This promotes equal
current sharing between paralleled devices.
6. Capability to withstand rated voltage and rated current simultaneously while
switching. This will eliminate the need for external protection (snubber)
circuit.
7. Large dv/dt and di/dt ratings. This will minimize the need of external
circuit; otherwise this ratings needed to be limited so that it do not damage
during operation in transient condition.
Gujarat Technological University, Ahmedabad 12
30. Christopher M Parmar 3.3. POWER CONVERTER TOPOLOGIES
3.3 Power Converter Topologies
3.3.1 Non-isolated Switch mode topologies
All the convertors used today can be derived from three basic topologies named :
1. Buck Converter
2. Boost Converter
3. Buck-Boost converter
Buck converter
In the basic buck circuit, transistor T1 is switched at higher frequency to produce
a chopped output voltage V2. This is then filtered by the L-C circuit to produce
a smooth load voltage Vo. The output voltage can be controlled by varying the
switching duty cycle.
The average output voltage is given by :
Vo =
ton
T
Vi
where: T = Total period
ton= Transistor on time
D = Transistor duty ratio
Figure 3.1: Buck Converter
Boost Converter
During the on-time of Transistor T1, the current builds up in the inductor L due
to the inductor voltage VL = Vi. When T1 is off, the voltage across L reverses
Gujarat Technological University, Ahmedabad 13
31. Christopher M Parmar 3.3. POWER CONVERTER TOPOLOGIES
(VL = Vi − Vo) and adds to the input voltage, making the output voltage greater
than the input voltage.
Vi.ton − (Vo − Vi) = 0
Vo = 1
1−D
Vi
Figure 3.2: Boost Converter
Buck-Boost Converter
The buck-boost DC-DC converter offers a greater level of capability than the
buck converter or boost converter individually. This configuration of a buck-boost
converter circuit uses the same number of components as the simple buck or boost
converters. However this buck-boost regulator or DC-DC converter produces a
negative output for a positive input.
The output voltage is given by the equation :
Vo = −
D
1 − D
Vi
Figure 3.3: Buck-Boost Converter
Gujarat Technological University, Ahmedabad 14
32. Christopher M Parmar 3.3. POWER CONVERTER TOPOLOGIES
3.3.2 Isolated Switch mode topologies
The non-isolated topologies are used for the application in which input to output
voltage ration does not differ by large factor. But when we want high output volt-
age gain, a transformer can be added between power stage and output stage for
the purpose of voltage scaling. The transformer is also act as electrical isolation
between input and output which leads to reduction of stresses in switching devices
and provision for multi output connections. All these topologies are derived from
basic buck or boost converter. Some of the examples are H-Bridge converter and
flyback converter.
H-Bridge Converter
In the bridge converter, transistors S1 and S3 conduct together, then transistor S2
and S3, thus producing a square ac voltage waveform equal to ±Vi on the trans-
former primary. The bridge converter is generally used in high power applications.
The output power from a bridge converter is double that from a half-bridge with
equally rated transistors.
The dc gain is :
Vo = 2.n.D.Vi
Figure 3.4: Full Bridge Converter
Gujarat Technological University, Ahmedabad 15
33. Christopher M Parmar 3.3. POWER CONVERTER TOPOLOGIES
Flyback Converter
During the transistor on time, circuit builds up a linear manner in the primary
circuit Vi = Ldi
dt
, storing energy (= 1
2
LI2
) in inductor. During this period, diode
D prevents any current flowing in the secondary. During the transistor off time,
the energy stored in the inductor is released to the load.
The output voltage is given by equation given below :
Vo =
n.D
1 − D
Vi
Figure 3.5: Flyback Converter
Gujarat Technological University, Ahmedabad 16
34. CHAPTER 4
Modelling, Design and Simulation
of Full-Bridge Driver for
Piezoelectric Actuator
4.1 Operation of Full-Bridge Topology
The proposed full bridge topology is shown in Figure 4.1. It includes four MOS-
FETs which re driven using Pulse width modulation(PWM). The major advantage
of using full bridge is that the voltage impressed across the primary is a square
wave of ±Vdc compared to ±Vdc/2 for the half bridge. Further, the maximum
transistor off-voltage stress is only the maximum dc voltage - same as half bridge.
Thus, for transistor of the same peak current and voltage ratings, the full bridge
is able to deliver twice the output power of the half bridge.
The circuit works as follows. Diagonally opposite transistors (S1 and S3 or S2 and
S4) are turned ON simultaneously during alternate half cycles. Assuming that
the drop of the transistor are negligible, the transformer primary is driven with
alternating polarity square wave of amplitude Vdc and on time ton. The output
voltage across load is give by Equation 4.1.
Vo = Vdc
Ns
Np
2ton
T
(4.1)
4.1.1 PWM generation
Pulse width modulation is basic method to control the output voltage of the
converter by varying width of the gate pulse. One of the method to generate
17
35. Christopher M Parmar 4.1. OPERATION OF FULL-BRIDGE TOPOLOGY
Figure 4.1: Full bridge driver for piezoelectric actuator
Table 4.1: Full bridge driver specification
Parameter Value
Input Voltage 200 VDC
Output voltage range -80 to 177V
Input average current 528mA
Output average current 680mA
Maximum output power 100 Watt
Switching frequency 10KHz
Operating frequency 100Hz
PWM is to compare high frequency triangular wave with fixed DC voltage as
shown in Figure 4.2. Other advanced multilevel PWM techniques[27,28,29,30,31]
are
also available that increases the output accuracy of the converter and reduces
harmonic distortion in inverter. Small dead band is provided as shown in Figure 4.3
between PWM and its inverted version and fed to opposite diagonal of bridge which
prevents short circuit. The dead band must be higher than rise time (tr) and fall
time(tf ) of MOSFET. Here, rise time of 2N6768 MOSFET is 190ns and fall time
is 130ns[32]
. So, chosen dead band is 1µs where switching frequency is 10KHz.
Figure 4.2: Conceptual diagram of PWM generation
Gujarat Technological University, Ahmedabad 18
36. Christopher M Parmar 4.2. SIMULATION AND RESULTS
Figure 4.3: PWM with dead band
4.1.2 Filter Circuit
The dc-dc convertor has fundamental advantage of high efficiency than linear am-
plifier, but there exist an important consideration of noise and ripple at their
output. Two noise sources are present in the output voltage, first at fundamen-
tal switching frequency and second at very high frequency which occurs during
switching transitions. LC filter is used in the design to reduce ripple in the output
voltage.
As resolution of the piezoactuator is very high (in terms of nanometer), small
change in output voltage results in actuation of the device. So the ripple of the
driver must exceed smallest detectable voltage change of piezoactuator. The given
piezoactuator produces displacement of 100nm when the voltage change is 178 mV.
For the sake of accuracy, we took desired output ripple is 50mV.
Vmax,ripple =
Xc
Xc + XL
VConverter,ripple (4.2)
where, Xc = 1
2πfsC
, and XL = 2πfsL. Here, fs is switching frequency of converter.
First step is to choose an inductor with a current rating double to the maximum
output current of the converter. The compromised value of the inductor for desired
voltage range is 3mH. By using Equation 4.2 we get Cmin = 337µF. The nearest
practical value is 440µF which is taken for simulations.
4.2 Simulation and Results
The proposed full bridge driver circuit was simulated in detail with OrCAD Cap-
ture CIS 16.6 software as shown in Figure 4.5. Firstly, the circuit was simulated
by giving SPWM (Sinusoidal Pulse Width Modulation) as the control signal to
MOSFET, to derive full voltage rage of the driver. The SPWM was generated by
Gujarat Technological University, Ahmedabad 19
37. Christopher M Parmar 4.2. SIMULATION AND RESULTS
comparing low frequency (here 100Hz) sine wave with high frequency triangular
wave (shown in Figure 4.4). The results in Table 4.4 shows full output voltage
swing of -80VDC to 177VDC for 100Hz operating frequency.
Figure 4.6 shows output voltage for 88% duty cycle which is 147V, for filter pa-
rameters L=3mH and C=440µF. The output ripple voltage is 55mV shown in
Figure 4.8 which is less than 178mV, the required resolution of piezoelectric actu-
ator. The current across inductor is shown in Figure 4.7. The list of values used
in this simulation is given in Table 4.2.
Table 4.3 shows the comparison of output voltage and current when filter param-
eters (i.e L and C) are changed to get required value of ripple voltage. As we
use higher value of inductor, the output current decreases, and circuit draws less
power but drawback is circuit becomes more bulkier due to large value of inductor.
So, Compromised value of capacitor and inductor must be used considering size
and efficiency.
Table 4.2: Circuit Parameters
Parameter Value
MOSFET 2N6768
Cpiezo 20 µF
L 3 mH
C 440 µF
L1 50 mH
C1 1 nF
R1 1 MΩ
Table 4.3: Filter parameters and Output Power comparison
L C Vin Iin(avg) Pin Vout Iout(avg) Pout
(mH) (µF) (V) (A) (W) (V) (A) (W)
5 220 200 0.291 58.2 146.949 0.355 52.16
3 440 200 0.528 105.6 147.993 0.6808 100.76
2 660 200 0.752 150.53 147.751 1.001 148.5
Gujarat Technological University, Ahmedabad 20
38. Christopher M Parmar 4.2. SIMULATION AND RESULTS
Figure 4.4: Sinusoidal Pulse Width Modulation generation
Figure 4.5: PSpice schematic of proposed full bridge driver
Figure 4.6: Output Voltage for Duty Cycle=88%
Table 4.4: Range of output voltage
VControl(V ) VOut(V )
4.5 -30
4.06 1
3.4 49.3
2.9 75.9
2.5 100
1.9 125
1.1 150
Gujarat Technological University, Ahmedabad 21
39. Christopher M Parmar 4.3. SUMMARY
Figure 4.7: Output current across inductor
Figure 4.8: Output Voltage ripple (55mV)
4.3 Summary
In this section, the high voltage full bridge driver is proposed to drive piezoactuator
load which is capable of driving piezoactuator with a voltage range of -20 V to 150
V. Filter parameters are optimized to get minimum ripple of 50 mV so that desired
resolution of the actuator can be achieved. To prevent short circuit, MOSFETs
are driven by PWM with dead band sufficiently higher than rise time and fall
time of MOSFET. 89.6 % efficiency is achieved for the proposed high voltage full
bridge driver.
Gujarat Technological University, Ahmedabad 22
40. CHAPTER 5
Modelling, Design and Simulation
of DC-DC Fly-back Converter
5.1 Introduction
The driving voltage of piezoelectric actuator is in terms of hundred of volts. As
the input voltage of the onboard power supply is in range of 24 VDC to 48 VDC,
a boost converter with high voltage gain is required to achieve driving voltage of
PEA.
Boost, buck-boost or flyback topology can be used as boost stage. But as
input voltage is very low and output voltage is so high, it is not advisable to use
boost or buck-boost topology. Flyback converters are used for application which
requires high output voltages but low power (≤ 5000V at < 15W). we can use it
for power rating up to 150W if DC supply voltages are high enough (≥ 160V ) so
that primary currents are not so high. Step up transformer allows to use low volt-
age MOSFET at the low voltage side so overall cost of the circuit is reduced. Also
when isolation is needed, Flyback converter is only the option. The operation
of flyback convertor, design parameters and simulation are discussed upcoming
sections.
23
41. Christopher M Parmar 5.2. OPERATION OF FLYBACK CONVERTER
Figure 5.1: Fly Back Converter
5.2 Operation of flyback converter
From the circuit diagram of Figure 5.1, when switch S is on, the primary winding
of the transformer is connected to the input supply with its dotted end connected
to the positive side. At the same time the diode D at secondary winding gets re-
verse biased because of the induced voltage in the secondary. Flyback transformer
is different than normal transformer. The winding polarity are reversed. Thus by
the turning on of switch ‘S’, primary winding will carry current but in secondary
winding there is no current flow because of the reverse biased diode.
(a) Current path (Operating in Mode-I) (b) Equivalent circuit
Figure 5.2: Operation of Mode 1
Figure 5.2 shows the current carrying part of the circuit and the circuit that is
functionally equivalent to the fly-back circuit during ON period. In the equivalent
circuit shown in Figure 5.2b, the conducting switch or diode is taken as a shorted
switch and the device that is not conducting is taken as an open switch.
In Figure 5.2b, the value of primary voltage is and secondary voltage will be
Gujarat Technological University, Ahmedabad 24
42. Christopher M Parmar 5.2. OPERATION OF FLYBACK CONVERTER
Vsec = Edc × N2
N1
and Vpri = Edc.
After conducting for some time period, when switch ‘S’ is turned off, the pri-
mary winding current path is broken and according to laws of magnetic induction,
the voltage polarities across the windings reverse. Reversal of voltage polarities
makes the diode in the secondary circuit forward biased. Figure 5.3a shows the
current path (in bold line) during ‘off’ period (left side) while right side one shows
the functional equivalent of the circuit during this period.
(a) Current path (Operating in Mode-II) (b) Equivalent circuit in Mode-2
Figure 5.3: Operation of Mode 2
In Figure 5.3b, the value of primary voltage is Vpri = Vo × N1
N2
and Vsec = Vo.
5.2.1 Design of Snubber circuit
The topologies which have a transformer in series with power MOSFET in series
(except buck converter), a huge amount of switching losses occur due to the over-
lap of falling current and rising voltage across the power transistor during turn off
interval. The integral I(t)V (t)dt over the turn off interval, generally have a very
large value. Even if averaged by the turn off duty cycle, it could be two to four
times large as transistor conduction loss. This loss increases at higher frequencies.
Circuits which reduces this loss at turn off is called turn-off snubber circuit. RCD
(Resistor, Capacitor and Diode) is one of the basic turn off snubber circuit which
is used in the proposed converter. Configuration of RCD snubber is Figure 5.4.
Gujarat Technological University, Ahmedabad 25
43. Christopher M Parmar 5.2. OPERATION OF FLYBACK CONVERTER
Figure 5.4: RCD snubber configuration
Operation
When switch ‘S’ base receives its turn off command, the transformer leakage in-
ductance attempts to maintain peak on current which had been flowing just before
the turn off command. This peak current divides in some way between off-turning
collector and C through diode D which has latched in.
The amount of current IC flowing into C slows up the collector voltage rise time,
and by making C large enough, the rising collector voltage and falling collector
current intersects so low down on the rising collector voltage waveform that tran-
sistor dissipation is decreased significantly. Selection of C has to be done first
to yield a sufficiently slow up collector voltage rise time, then value of R is cal-
culated to discharge C to within 5 % of its full charge in minimum ton given by
Equation 5.1.
3RC = ton(min) (5.1)
The power dissipation in R in Watts is
PDR =
0.5C(2Vdc)2
T
(5.2)
The value of capacitor can be calculated from Equation 5.3:
C =
(Ip/2)tf
2Vdc
(5.3)
where tf is fall time of MOSFET. and from Equation 5.1
R =
ton(min)
3C
(5.4)
Gujarat Technological University, Ahmedabad 26
44. Christopher M Parmar 5.3. SYSTEM DESIGN AND MODELING
Table 5.1: Design Parameters of Flyback converter
Design parameter Value
Input voltage (Vdc) 24 VDC
Output voltage (Vout) 200 VDC
Desired Output Power (Po) 50 W
Switching Frequency (fs) 100 KHz
5.3 System Design and Modeling
The proposed flyback convertor design parameter is modeled with 50 W output
power, high frequency PWM to drive MOSFET, high frequency transformer, snub-
ber circuit across power MOSFET, output rectifier diode, output capacitor. The
onboard power supply is 24 VDC and desired output voltage is 200 VDC. The
design parameters of proposed system is given in Table 5.1.
5.3.1 Output Load :
As output power is 50 W,
R =
V 2
Pout
= 800Ω
(5.5)
5.3.2 Establishing primary/secondary turns ratio :
The primary to secondary turns ratio Np
Nsm
determines the maximum off voltage
stress Vsm on the power transistor which is given by Equation 5.6.
Vms = Vdc + VR + VSpike (5.6)
Vms = Maximum off-voltage stress on the power MOSFET, VR is Reflected voltage
which is given by Np
Nsm
Vo and Vspike = 30% of Vdc.
Now Np
Nsm
= Vout
Vin
= 200
24
= 8.33. So from equation Equation 5.6, maximum off
voltage stress is 55 V.
Gujarat Technological University, Ahmedabad 27
45. Christopher M Parmar 5.3. SYSTEM DESIGN AND MODELING
5.3.3 Determine maximum ON Time(Ton) :
To ensure that the circuit remains in discontinuous conduction mode, the maxi-
mum ON time which will generate the desired maximum output power is establish
thus :
TON + Tr = 0.8T
Where, TON = Maximum ON time and Tr = T − TON
TON =
(Vo + 1)(Np/Nsm
)(0.8T)
(Vdc − 1) + (Vo + 1)(Np/Nsm
)
= 4.09µS
(5.7)
5.3.4 Primary Inductance (Lp):
The equation of primary inductance in terms of output resistance and DC input
voltage is given in Equation 5.8.
Lp =
Ro
2.5T
(
VdcTON
Vo
)2
=
(VdcTON )2
2.5TP0
= 7.708µH
(5.8)
5.3.5 Secondary Inductance (Ls):
The secondary inductance is given by equation Equation 5.9.
Ls = (
Ns
Np
)2
Lp
= 0.534mH
(5.9)
5.3.6 Transistor Peak Current(Ip) :
The peak current of the transistor is given in
Ip =
VdcTON
Lp
= 12.734A
(5.10)
where Vdc is specified and TON is calculated from Equation 5.7.
Gujarat Technological University, Ahmedabad 28
46. Christopher M Parmar 5.3. SYSTEM DESIGN AND MODELING
5.3.7 Primary RMS current and wire size
Primary current is a triangle of peak amplitude Ip at a maximum duration Ton
out of every period T. The RMS value of primary current is :
Irms(primary) =
Ip
√
3
TON
T
= 4.7A
(5.11)
where, Ip and Ton are given from Equation 5.10 and Equation 5.7.
At 500 circular mils per RMS ampere, the required circular mils (primary)=
500Irms(primary) = 2350.
5.3.8 Secondary RMS current and wire size
Secondary current is a triangle of peak amplitude Is = (Ns
Np
)Ip and duration Tr =
T − TON .
Secondary RMS current is given by,
Irms(secondary) =
Ip(Np/Nsm
)
√
3
Tr
T
= 0.6782A
(5.12)
where, Tr = T − TON .
At 500 circular mils per RMS ampere, the required circular mils Secondary circular
mills required = 500Irms(secondary) = 339.11 ≈ 340.
5.3.9 Output capacitor
Output capacitor is chosen on the basis of specified output ripple. The ripple
voltage is given by Vripple = IoutTr
Co
. So,
Co =
IoutTr
Vripple
(5.13)
If desired output ripple voltage is 0.05 V, then we get output capacitor value as
29.55µF ≈ 30µF.
5.3.10 Snubber circuit parameters :
From Equation 5.3, the value of capacitor,
Gujarat Technological University, Ahmedabad 29
47. Christopher M Parmar 5.4. SIMULATION RESULTS
C =
(12.734/2)90 × 10−9
2 × 24
= 11.9 × 10−9
F
and from Equation 5.4,the value of resistor,
R =
4.09 × 10−6
3 × 11.9 × 10−9
≈ 115Ω
5.4 Simulation Results
The PSpice schematic diagram of proposed flyback converter is shown in Fig-
ure 5.5. The circuit is simulated in OrCad Capture 16.6 for 100 ms time duration
and the output waveform are plotted. Waveform of Output voltage is plotted in
Figure 5.6. The desired output voltage is 200 V, the simulated result shows output
voltage is 201.2 V. The error between desired and simulated is very small. The
desired output voltage ripple is 50 mV, but as we have used practical value of ca-
pacitor, the obtained value of output ripple is 45 mV. The calculated peak current
at drain of MOSFET is 12.734 A from Equation 5.10, the obtained value of MOS-
FET drain peak current is 12.86 A which is very near to theocratical value. After
performing power calculation, the obtained efficiency is 71.88 %. The simulation
was also done without using snubber circuit, in that case the obtained efficiency
was 53.2 %. So we can conclude that using RCD snubber circuit, the losses in
the MOSFET can be significantly reduced. The comparative waveform of input
current, output current and output voltage is shown in Figure 5.9. All converter
parameters are listed in Table 5.2.
Gujarat Technological University, Ahmedabad 30
48. Christopher M Parmar 5.4. SIMULATION RESULTS
Table 5.2: Simulated Parameters of Flyback converter
Design parameter Value
Maximum Input voltage (Vdc) 24 VDC
Maximum Output voltage (Vout) 201 VDC
Input average current (Idc) 3.92 A
Output average current (Iout) 0.3 A
Input Power (Pin) 83.7 W
Output Power (Po) 60.2 W
Efficiency 71.8 %
Switching Frequency (fs) 100 KHz
Figure 5.5: PSpice schematic of Flyback topology
Figure 5.6: Output Voltage across load
Gujarat Technological University, Ahmedabad 31
49. Christopher M Parmar 5.5. SUMMARY
Figure 5.7: Output Voltage ripple across load
Figure 5.8: Input Peak current
Figure 5.9: Input average current,Output Voltage and Output Current
5.5 Summary
In this section, modeling, design and simulation of dc-dc flyback converter is pre-
sented to boost onboard supply. This converter is capable of driving piezoelectric
driver of 200V input voltage. The power rating of the converter is 50 W. The
proposed flyback converter uses MOSFET as switch at primary side which is
driven by 100 KHz PWM. All the circuit parameters are calculated to get optimal
value of output parameters. RCD snubber circuit is used to reduce power losses
MOSFET. The circuit is analysed with and without using snubber circuit. The
obtained efficiency of the converter is 71.88 %.
Gujarat Technological University, Ahmedabad 32
50. CHAPTER 6
Digitally Controlled PWM
Generation Using FPGA
6.1 Design flow on FPGA
The Field Programmable Gate Array (FPGA) is a array of logic cells which can
be reprogrammed depending upon the requirement of the user. The time to the
market for design based on FPGA is very small because of its highly reconfig-
urability. Embedded systems which are designed based on FPGAs have very less
Manufacturing and prototyping cost compared to other designs.
Figure 6.1 shows the sequence of steps followed when implementing PWM Gener-
ator design on FPGA. These steps are discussed in detail here. One of the most
important advantages of FPGA based design is that users can design it using CAD
tools provided by design automation companies. Generic design flow of an FPGA
includes following steps:
ˆ System Design
At this stage designer has to decide what portion of his functionality has to
be implemented on FPGA and how to integrate that functionality with rest
of the system.
ˆ I/O integration with rest of the system
Input Output streams of the FPGA are integrated with rest of the Printed
Circuit Board, which allows the design of the PCB early in design process.
FPGA vendors provide extra automation software solutions for I/O design
33
51. Christopher M Parmar 6.1. DESIGN FLOW ON FPGA
Figure 6.1: FPGA Design Flow
process.
ˆ Design Description
Designer describes design functionality either by using schematic editors or
by using one of the various Hardware Description Languages (HDLs) like
Verilog or VHDL.
ˆ Synthesis
Once design has been defined CAD tools are used to implement the design on
a given FPGA. Synthesis includes generic optimization, slack optimizations,
power optimizations followed by placement and routing. Implementation
includes Partition, Place and route. The output of design implementation
phase is bit-stream file.
ˆ Design Verification
Bit stream file is fed to a simulator which simulates the design functionality
and reports errors in desired behavior of the design. Timing tools are used to
determine maximum clock frequency of the design. Now the design is loading
onto the target FPGA device and testing is done in real environment.
Gujarat Technological University, Ahmedabad 34
52. Christopher M Parmar 6.2. PWM DESIGN IMPLEMENTATION
Figure 6.2: Example Implementation
6.2 PWM design implementation
6.2.1 Introduction
This section includes Pulse width modulation (PWM) block which can be im-
plemented in CPLDs, EPLDs and FPGAs, it is written in VHDL programming
language. The duty cycle of the output PWM can be changed by user logic. The
center of each pulse happens at the PWM frequency, also the width varies around
the center. When the phases are set to more than one, the PWM block will gen-
erate PWM signal for each phase. The designing was done in Libero IDE v9.1
software. The simulation was done in ModelSim ME 10.3c. Figure 6.2 shows a
PWM generator block which was designed.
6.2.2 Theory of Operation
The system clock pulses in PWM period is given by system clock/PWM frequency.
For each phase, counters defines this period. We have allocated one counter for
each phase and its values are offset by phase. Counters are incremented on each
pulse of system clock and when it reaches to end of period, it clears its value.
The duty cycle shows the points in whole period during which transition from high
to low and low to high occurs. Figure 6.3 shows the basic idea used to determine
these positions. The signal’s falling edge occurs at 50% duty cycle, and its rising
edge occurs at the end of the period minus 50% duty cycle. When the counter
reaches each of these positions, the PWM signal makes transition to high to low
or low to high. As we know that half duty cycle will never exceed a half period of
switching frequency, so falling edge will always occur before the rising edge.
Gujarat Technological University, Ahmedabad 35
53. Christopher M Parmar 6.2. PWM DESIGN IMPLEMENTATION
Figure 6.3: PWM waveform with period and half duty cycle
Table 6.1: Generic Parameters
Generic Data Type Description
sys clk Integer System clock frequency
(Hz)
pwm freq Integer Frequency of PWM in
Hz
bits resolution Integer The number of bits to
represent the duty cycle
phases Integer Number of PWM out-
puts
6.2.3 Configurable Parameters
Four GENERIC parameters are used to configure the PWM block which is shown
in Table 6.1. sys clk is system clock which is set by user. pwm freq is the
switching frequency of PWM. This value has to be calculated based on sys clk.
bits resolutions parameter indicates number of bits used to generate PWM. If it
is set to 8 then PWM resolution is 256. We can adjust this parameter to get finest
width possible. phases parameter indicates number of phases generated by the
PWM block. If it is set to 3 then 3 PWM output will be generated at pwm out
each separated 120 degree apart.
Since the PWM period is defined in system clocks as sys clk/pwm freq, this
ratio also affects the duty cycle resolution. A duty cycle resolution is not achiev-
able if it exceeds the number of system clocks in the PWM’s period. Similarly,
the achieved duty cycle is subject to single bit rounding errors if the period is not
an integer multiple of the resolution.
Gujarat Technological University, Ahmedabad 36
54. Christopher M Parmar 6.3. SIMULATION RESULTS
Table 6.2: Description of Port
Port Width Mode Data Type Interface Description
clk 1 in standard
logic
user logic system clock
reset n 1 in standard
logic
user logic Asynchronous
active low
reset
ena 1 in standard
logic
user logic 0: current
duty cycle .
1: latches in
the new duty
cycle.
duty 8 in standard
logic vector
user logic New duty cy-
cle.
pwm out 2 out standard
logic vector
load Output
PWM
signals.
The PWM
changes its
duty cycle
around the
center of the
the pulse.
6.2.4 Port Descriptions
6.2.5 Controlling the Duty Cycle
It is possible to control the duty cycle from the user logic by latching new duty
cycle on ’duty’ port. When ena port is set to ’1’, PWM generator will latch new
duty cycle. Figure 6.4 shows a ModelSim simulation for two different duty cycles.
First 0x80 value shows 50% duty cycle which is changed to 75%, but it will not
latch new duty cycle until ena port changes to ’1’.
6.2.6 Reset
The default value for resetn is logic high. For logic low, PWM generator compo-
nent will not work as it will asynchronously reset the component. As we reset,
PWM logic component will clear period counters and it will also set both PWM
outputs to ’0’.
6.3 Simulation Results
The above code was simulated in ModelSim ME 10.3c and the simulation results
are shown in Figure 6.4. As shown in the figure, the new duty cycle is latched at
Gujarat Technological University, Ahmedabad 37
55. Christopher M Parmar 6.4. HARDWARE IMPLEMENTATION
the output port when ena signal changes from 0 to 1. Also the results shows 50%
and 75% duty cycle PWM with 8 bits of resolutions.
6.4 Hardware Implementation
The PWM was generated using ProASIC3 starter kit. The kit is composition of
many onboard peripherals like LEDs, four push buttons, two hex switch, LCD
port, SMA connector for external clock and powerful ProASIC3E1500 FPGA in
PQFP208 package. Figure 6.5 shows photograph of ProASIC3 Starter kit. Push
button was used as ena signal to latch new duty cycle. There are two hex switched
onboard which are used to control 8 bit resolution duty cycle of PWM. Figure 6.6
shows schematic diagram of hex switch. To use those two switches, all correspond-
ing jumpers are shorted so that it will be connected to the input port of FPGA
chip. Then using I/O Attribute Editor toolbox in Libero IDE, the pin assignment
was done as shown in Figure 6.7.
PWM generation code was compiled in Libero IDE software. After generating
programming file, the same was downloaded in FPGA chip using FlashPro4 pro-
grammer. PWM signal was generated on pin number 175 and it was measured
using Tektronix MSO4104. The results in figure 6.8a shows 25% duty cycle PWM
with 10 KHz frequency and figure 6.8b shows PWM with 50% duty cycle.
(a) 25% duty cycle (b) 50% duty cycle
Figure 6.8: PWM generation using ProASIC3E kit
Gujarat Technological University, Ahmedabad 38
56. Christopher M Parmar 6.4. HARDWARE IMPLEMENTATION
Figure6.4:SimulationofChangingtheDutyCycle
Gujarat Technological University, Ahmedabad 39
57. Christopher M Parmar 6.4. HARDWARE IMPLEMENTATION
Figure 6.5: ProASIC3/E Development Kit
Figure 6.6: Hex Switch Schematic
Figure 6.7: I/O Attribute Editor Window
Gujarat Technological University, Ahmedabad 40
58. CHAPTER 7
Development of a Laboratory
Prototype of Reduced Scale Full
Bridge dc-dc Converter
7.1 Introduction
In chapter 4 , the full bridge driver for piezoelectric actuator is discussed with its
modelling, design and simulations. In this chapter, the development of laboratory
prototype of reduced scale full bridge driver and its test results are presented.
MOSFET driving waveform are also presented with all the voltage levels. It also
discusses the efficiency analysis of the fabricated circuit.
7.2 Experimentation Methodology
An experimental prototype of full bridge driver was fabricated to produce output
of 18V for 4.7 µF capacitive load at switching frequency of 10 KHz. The reduced
scale circuit was fabricated as per the availability of the components in the lab-
oratory. The chosen MOSFET is from International Rectifier. The component
values and ratings are listed in Table 7.1. The high side and low side drive signal
for MOSFETs was generated using MOSFET driver IC HIP4080A[33]
, which can
drive full bridge configuration of MOSFET. The PWM signal for the driver IC
was generated using FPGA PROASIC3E1500 development kit[34]
. The design and
generation of PWM was discussed in chapter 6. All the components used in the
fabrication process are space qualified components.
41
59. Christopher M Parmar 7.3. FULL POWER CIRCUIT
Table 7.1: Experimental parameters and components
parameter Value
Input voltage (Vdc) 18 VDC
Switching Frequency (fs) 10 KHz
MOSFET IRfZ44N, 50 VDSS, ID = 8 A
Resister (for Filter) 100 Ω
Capacitor (for Filter) 150 µ F, 30V
Bootstrap Diodes 1N7040
MOSFET Driver HIP4080AIPZ
7.3 Full Power Circuit
7.3.1 Drive circuit for MOSFETs
HIP4080AIPZ ic was used as h-Bridge MOSFET driver. This ic is able to pro-
vide maximum of 95VDC bootstrap voltage. The operating range is 10VDC to
95VDC. The schematic diagram of driver circuitry of full bridge converter is shown
in Figure 7.1. There are two option for driving high side MOSFETs, i.e bootstrap-
ping mechanism and charge pump mechanism. To some extent , charge pump is
able to provide charge to high side MOSFETs and we can eliminate design of
bootstrapping circuit. But for other high voltage and high frequency applications,
bootstrapping circuit is must. It provides instantaneous current needed for turn-
ing on the power switch and charge pump provides enough current to “maintain”
bias voltage across MOSFET gate to source.
Input Logic
There are two input pins (IN+ and IN-)to control the output PWM. There is also
one pin available ’out’ which can provide compensation or hysteresis. With the use
of ’DIS’ pin, we can disable all the MOSFETs gate drive regardless whatever the
input command is. ’HEN’ pin , known as “High enable” is used to enable (High
signal) or disable (Low signal) both high side MOSFETs. If we want to drive both
upper and lower drivers, HEN pin ha continuously held to high. Table 7.2 shows
the truth table logic to operate driver ic in different modes.
Gujarat Technological University, Ahmedabad 42
60. Christopher M Parmar 7.3. FULL POWER CIRCUIT
Figure7.1:DriverCircuitforMOSFET
Gujarat Technological University, Ahmedabad 43
61. Christopher M Parmar 7.3. FULL POWER CIRCUIT
Table 7.2: Input Logic Truth Table
in+ >
in−
HEN UV DIS ALO AHO BLO BHO
x x x 1 0 0 0 0
0 0 0 0 1 0 0 0
1 1 0 0 0 1 1 0
0 1 0 0 1 0 0 1
1 0 0 0 0 0 1 0
x x 1 x 0 0 0 0
Propagation Delay Control
Propagation delay control is a major feature of the HIP4080A. Two identical sub-
circuits within the IC delay the commutation of the power MOSFET gate turn-on
signals for both A and B sides of the H-bridge. The gate turn-off signals are not
delayed. We can tailor the low side to high side commutation delay times by plac-
ing a resistor from the HDEL pin to the VSS pin. Similarly, a resistor connected
from LDEL to VSS controls the high side to low side commutation delay times of
the lower power switches. The HDEL resistor controls both upper commutation
delays and the LDEL resistor controls the lower commutation delays. The delay
is added to the falling edge of the “off” pulse associated with the MOSFET which
is being commutated off. When the delay is complete, the “on” pulse is initiated.
This has the effect of “delaying” the commanded on pulse by the amount set by
the delay, thereby creating dead-time. The value of HDEL and LDEL can be
tuned to get desired value od dead-time. As per the datasheet, the maximum
value of dead band provided by HIP4080A is 120ns at 250 KΩ.
GATE DRIVE REQUIREMENTS OF HIGH-SIDE DEVICES
The gate drive requirements for a power MOSFET or IGBT utilized as a high-
side switch (the drain is connected to the high voltage rail, as shown in Figure 1)
driven in full enhancement (i.e., lowest voltage drop across its terminals) can be
summarized as follows:
1. Gate voltage must be 10 V to 15 V higher than the source voltage. Being
a high-side switch, such gate voltage would have to be higher than the rail
voltage, which is frequently the highest voltage available in the system.
2. The gate voltage must be controllable from the logic, which is normally
Gujarat Technological University, Ahmedabad 44
62. Christopher M Parmar 7.3. FULL POWER CIRCUIT
referenced to ground. Thus, the control signals have to be level-shifted to
the source of the highside power device, which, in most applications, swings
between the two rails.
3. The power absorbed by the gate drive circuitry should not significantly affect
the overall efficiency.
Bootstrap Bias Supply Circuit Design
One of the most widely used methods to supply power to the high-side drive cir-
cuitry of a gate driver IC is the bootstrap power supply. The bootstrap power
supply consists of a bootstrap diode and a bootstrap capacitor.
The bootstrap circuit works as shown in Figure 7.2. When the Vs goes below IC
Figure 7.2: Bootstrap Power Supply Circuit[35]
supply voltage VDD or is pulled down to ground (the low side switch is turned
on and high side switch is turned off) , the bootstrap capacitor CBOOT , charges
through bootstrap resistor RBOOT , bootstrap diode DBOOT , from the VDD power
supply as shown in Figure 7.2. This is provided by VBS when Vs is pulled by a
higher voltage by the high side switch, the VBS supply floats and the bootstrap
diode reverse biases and blocks the rail voltage (the low side switch is turned off
and high side switch is turned on), from the IC supply voltage, VDD.
Gujarat Technological University, Ahmedabad 45
63. Christopher M Parmar 7.4. HARDWARE PROTOTYPE
CBS =
QG + QRR + (
IDR+IQBS
fP W M
)
VBS1 − VBS2
(7.1)
where,
IDR= Bootstrap diode reverse leakage current
IQBS = Upper supply quiescent current
QRR = Bootstrap diode reverse recovered charge
QG = Turn-on gate charge transferred
fPWM = PWM operating frequency
VBS1 = Bootstrap capacitor voltage just after refresh
VBS2 = Bootstrap capacitor voltage just after upper turn on
CBS = Bootstrap capacitance
Equation 7.1 describes the relationship between the gate charge transferred to
the MOSFET upon turn-on, the size of the bootstrap capacitor and the change in
voltage across the bootstrap capacitor which occurs as a result of turn-on charge
transfer.
For IRFF130 power MOSFET, the data book states a gate charge, QG, of 12.8nC
typical and 28.5nC maximum, both at VDS = 50V. Using the maximum value of
28.5nC the maximum charge we should have to transfer will be less than 28.5nC.
For 1N7040, 200V, fast recovery rectifier, reverse recovery time is 150ns. Since the
recovery current waveform is approximately triangular, the recovery charge can be
approximated by taking the product of half the peak reverse current magnitude
(1A peak) and the recovery time duration (150ns). In this case the recovery charge
should be 75nC. Since the internal charge pump offsets any possible diode leakage
and upper drive circuit bias currents, these sources of discharge current for the
bootstrap capacitor will be ignored. so,
CBS =
28.5nC + 75nC
12V − 11V
= 103nF ≈ 0.1µF
7.4 Hardware Prototype
The hardware prototype of the schematic shown in Figure 7.1 was fabricated for
testing the driver circuit. Figure 7.3 shows the component side and solder side of 4
Gujarat Technological University, Ahmedabad 46
64. Christopher M Parmar 7.4. HARDWARE PROTOTYPE
layer bare PCB. Figure 7.4 shows the component mounted PCB. The biasing sup-
ply for the H-Bridge converter is given from 9-pin connector as shown in Figure 7.4.
All the input logics and biasing for driver IC is given from test points shown below
9-pin connector in Figure 7.4. Both the biasing has sufficient decoupling capac-
itors mounted onboard to surpass power supply fluctuations. Figure 7.5 shows
schematic diagram of LLC filter used in the circuit. As the available value of the
inductor was 37µH, the equivalent capacitor value was calculated using equation
Equation 4.2 which is 220 µF. The Maximum available value of the capacitor
in the laboratory is 150 µF at 30V polarized capacitor, so to increase voltage
capacity as well as capacitor value , series parallel combination was done which
results in the capacitor bank as shown in Figure 7.5b. The same was fabricated
in the laboratory as shown in Figure 7.6.
(a) Component side (b) Solder side
Figure 7.3: Bare PCB for H-Bridge dc-dc converter
(a) Typical RC filter (b) Practical RC filter
Figure 7.5: RC filter circuit schematic
Gujarat Technological University, Ahmedabad 47
65. Christopher M Parmar 7.5. TEST RESULTS
Figure 7.4: Assembled PCB- Component side
7.5 Test Results
Hardware prototype model was fabricated in the laboratory which is shown in
Figure 7.7. H-Bridge and driver IC power supply were given through high quality
power supply available in the laboratory. The voltage waveform measurements
were taken using TEKTRONIX P6248 differential prob. The current waveform
measurements were taken using Tektronix TCP0030 current probe. Active/Pas-
sive ground terminated voltage probes cannot be used for the measurement of high
side MOSFETs of H-bridge as the source of high side MOSFETs are at floating
point. All waveforms are recorded on TEKTRONIX MSO4104 1GHz, 1 GS/s
Mixed Signal Oscilloscope. PWM to the IN+ of HIP4080 ic was given from the
PROASIC3E1500 Development kit which was discussed in detailed in Chapter 6.
IN- pin was connected to constant 2V power supply.
7.5.1 HO and LO waveform
As we give PWM to the input of the driver IC, it generates HO and LO signals.
Figure 7.8 shows voltage across high side MOSFET gate to source terminal. It
is having differential 4V amplitude which is sufficient to turn ON the high side
Gujarat Technological University, Ahmedabad 48
66. Christopher M Parmar 7.5. TEST RESULTS
Figure 7.6: Filter Capacitor Bank
MOSFET. When we measure HO MOSFET source to ground terminal voltage, it
shows 23V amplitude. So according to bootstrap principal voltage at gate of high
side MOSFET is addition of bootstrap voltage and H-bridge supply. Figure 7.9
shows voltage across low side MOSFET gate and ground terminal. It is having
11.6V amplitude which is sufficient to turn ON the low side MOSFET. Both HO
and LO signals have very small transition time. Figure 7.10 shows HO and LO
waveform simultaneously with respect to PWM signal. Figure 7.11 shows the
voltage across bootstrap capacitor. It is clearly visible that capacitor is able to
hold the charge once it is charged when low side MOSFET is ON and high side
MOSFET is OFF. The bootstrap capacitor voltage is around 15V.
Gujarat Technological University, Ahmedabad 49
67. Christopher M Parmar 7.5. TEST RESULTS
Figure7.7:Experimentalsetup
Gujarat Technological University, Ahmedabad 50
68. Christopher M Parmar 7.5. TEST RESULTS
Figure 7.8: High side MOSFET gate to source voltage
Figure 7.9: High side MOSFET gate to source voltage
Gujarat Technological University, Ahmedabad 51
69. Christopher M Parmar 7.5. TEST RESULTS
Figure 7.10: HO and LO signal with respect to PWM signal from FPGA(From top-
(1)PWM (2)HO (3)LO (4) Comparator Output)
Figure 7.11: Voltage across bootstrap capacitor (From top-(1)VBS (2)Comparator
Output)
7.5.2 Propagation Delay Between HO and LO
The logic behind propagation delay was discussed in section section 7.3.1. When
the circuit is tested, it was found that at 10KHz switching frequency, the delay
between HO falling edge and LO rising edge was 750ns , and the delay between HO
rising edge and LO falling edge was 148ns. This delays are not symmetric because
Gujarat Technological University, Ahmedabad 52
70. Christopher M Parmar 7.5. TEST RESULTS
gate turn-off signal is not delayed but gate turn-on signal is delayed. These delays
are enough to provide dead band between turn-on and turn-off of high side and
low side MOSFETs as IRFZ44N MOSFET have 14ns of tun-on delay time and
45ns of turn-off delay time which is far less than the delay we have achieved[36]
.
Figure 7.12: Dead band period between HO falling and LO rising edge(From top-
(1)HO (2) LO)
Figure 7.13: Dead band period between HO rising and LO falling edge(From top-
(1)HO (2) LO)
Gujarat Technological University, Ahmedabad 53
71. Christopher M Parmar 7.5. TEST RESULTS
7.5.3 Output Voltage across Load
A non-polarized capacitor of 4.7µF was connected as highly capacitive load at
the output of RC filter instead of piezoelectric actuator for testing purpose. Fig-
ure 7.14 shows the ripple in output voltage. The measured value of output ripple
was 265mV. By fine tuning the filter parameters, this ripple value can be reduced
further. Figure 7.15 shows the current waveform when measured using current
probe at load capacitor. It is shown in zoomed waveform of Figure 7.16 that the
peak current value of output capacitor is around 70mA which is due to charging
of output capacitive load on switching of MOSFETs. In addition to this , current
waveform of HIP4080 ic and H-bridge supply is also plotted in Figure 7.17 and
Figure 7.18 which shows that the circuit takes only transient current because of
highly capacitive behaviour of load.
Figure 7.14: Ripple voltage across load(From top-(1)Vripple (2)Comparator Output
(3) Trigger source)
Gujarat Technological University, Ahmedabad 54
72. Christopher M Parmar 7.5. TEST RESULTS
Figure 7.15: Current at output load(From top-(1)Comparator Output (2) ILoad)
Figure 7.16: Zoomed waveform of current at output load (From top-(1)Comparator
Output (2) ILoad)
Gujarat Technological University, Ahmedabad 55
73. Christopher M Parmar 7.5. TEST RESULTS
Figure 7.17: MOSFET driver IC power supply current (From top-(1)Comparator
Output (2) IDriver Supply)
Figure 7.18: H-Bridge power supply current (From top-(1)Comparator Output (2)
IHB Supply)
7.5.4 Duty Ratio to Output Voltage relation
As we change duty cycle using hex switch on FPGA kit, the output voltage across
load capacitor also varies. The voltage was tabulated against different duty cycles
in Table 7.3. As shown in the table, it is possible to get positive as well as negative
voltage across non-polar capacitive load which is the basic drive requirement of
Gujarat Technological University, Ahmedabad 56
74. Christopher M Parmar 7.5. TEST RESULTS
piezoelectric actuator. The same results were plotted as shown in Figure 7.19
which concludes highly linear behaviour of H-Bridge driver circuit.
Table 7.3: Duty Cycle vs Output Load Average Voltage
Duty Cycle (%) Average Output Voltage (V)
6.2 -12.85
10 -11.5
16.3 -9.51
20 -8.25
26.3 -6.17
30 -5.55
36.3 -4.07
40 -2.77
46.5 -0.74
50 0.023
63 2.55
70 5.45
75 6.68
80 7.62
85 9.45
Figure 7.19: Duty cycle vs Average output voltage graph
7.5.5 Efficiency Analysis
For fixed duty cycle at 80%, input and output power can be calculated. The input
supply of H-Bridge was 18V and input average current was 76.47mA. So, input
power is 1.376 Watt. As we measure output voltage at 80% duty cycle, it was
7.2V and output average current across load was 126mA, so output power is 0.921
Gujarat Technological University, Ahmedabad 57
75. Christopher M Parmar 7.6. SUMMARY
Watt. So according to the formula, efficiency = (Output Power/Input Power), we
get 66.93 % efficiency.
Table 7.4: Circuit Input and Output Power Characteristics
Voltage Current
H-Bridge Supply 18V 53 mA
Driver Supply 12V 10mA
Load Capacitor 7.2V 126mA
7.6 Summary
In this chapter, fabrication details of reduced scale H-Bridge driver was discussed
with all its parameters. The circuit was tested in different input conditions. All the
characteristic waveform of the circuit was plotted and discussed in detail. We got
desired linear amplifer characteristics as plotted and discussed in this chapter. The
efficiency of the circuit was obtained as 66.92%. By fine tuning filter parameters
and proper selection of the components , it is possible to achieve high efficiency.
Gujarat Technological University, Ahmedabad 58
76. CHAPTER 8
Conclusion
The main objective of this dissertation is to design, develop and test the drive
electronics for piezoelectric actuator. The study was motivated by the need to
provide efficient actuation system for the purpose of mirror positioning of satellite
telescope camera system.
The research work has covered the following major sections:
(a) Detailed design and simulation of high voltage full bridge driver for piezoelec-
tric actuator
(b) Detailed design and simulation of flyback boost converter to boost onboard
power supply to get high output voltage
(c) Construction of laboratory prototype of reduced scale full bridge driver for
piezoelectric actuator
(d) Generation of digitally controlled Pulse Width Modulation(PWM) using FPGA
The main conclusion related to this work are summarized as below :
8.1 Main Conclusions
ˆ As per the literature survey, full bridge driver is efficient drive technique for
piezoelectric actuators. This report includes modeling, design of parameters
and OrCad Capture simulations of open loop high voltage H-Bridge driver.
The filter parameter are also calculated to get lowest ripple at the output
59
77. Christopher M Parmar 8.2. FUTURE SCOPE
stage so that desired resolution accuracy can be met. Dead band in PWM
is used to avoid shorting of the circuit ultimately decreasing switching losses
and increasing efficiency. After doing power calculation and loss analysis we
achieved 89.6% efficiency for proposed driver. The switching and conduction
losses in the MOSFETs are very less.
ˆ It also includes modeling, design and simulations of open loop dc-dc flyback
converter. Snubber circuit is used to minimize switching and conduction
losses in MOSFET. The circuit is analysed with and without using snubber
circuit. The obtained efficiency of the converter is 71.88 %.
ˆ A laboratory prototype of reduced scale full bridge driver was developed to
drive 4.7 µF capacitive load at 10 KHz switching frequency using power
MOSFETs with Rds(ON) as low as 17.5 mΩ. For switching of MOSFET,
HIP4080 H-Bridge driver IC was used. The varying duty cycle PWM with 8
bit resolution was generated by PROASIC3E1500 development kit. The H-
Bridge driver was tested for 18V biasing voltage and 10% to 90% duty cycle.
At 70% duty cycle , the fabricated circuit was able to give 66% efficiency.
The output voltage ripple was measured as 280 mV.
8.2 Future Scope
1. By tuning filter circuit parameters, the output voltage ripple can be reduced
further to get higher resolution of displacement of piezoelectric actuator.
2. By adding negative feedback loop in above circuit, it is possible to get full
control over the displacement of the actuator. The position error of the
actuator can be sensed and corrected.
3. By using full scale components, it is possible to develop full scale driver for
piezoelectric actuator as discussed in chapter 3.
Gujarat Technological University, Ahmedabad 60
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