Question 2: Write the complete VHDL code for the 4-to-1 multiplexer in Figure 2 using the with-select instruction and enable. Use the name mux4_1 as the design entity. Note: E is a 1-bit control signal (input port), S is a 2-bit input selection bus (input port), D is a 4-bit data bus (input port), and Y is a 1-bit data signal (output port). Figure 2, 8 [Show complete multiplexer VHDL code including entity and architecture].