- The simulation shows the peak current in the bridge diode D1 at startup, which reaches around 140A.
- This occurs when the power supply is first turned on before it reaches steady state operation.
- The high current is due to the initial charging of the transformer primary from the DC bus capacitor.
- Over time, the current decreases as the power supply components become energized and regulated operation begins.
4. 1.1 Output voltage
• Simulation result confirming that the output voltage would be 19 Volt at 5-A load. The
result also shows that the circuit need 60ms to reach steady state.
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5. 1.2 Output current
• Simulation result confirming that the output current would be 5 Amp. The result also
shows that the circuit need 60ms to reach steady state.
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6. 1.3 Output ripple voltage
• Simulation results shows the output ripple voltage at maximum current load
(approximately 17.5mVP-P).
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7. 1.4 Step-load response
• Simulation results shows waveform of the output voltage responding to stepping
current 3/5A.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 7
8. 2.Basic operation of switching power supply using FA5541
T1 D1
Id
OFF
M1
ON +
OUT Cd
0 0 Vds
RZCD
ZCD
RS -
CZCD
K
0
REF
0
A
IS
+ 0
FB
V(RS) = Id*RS
-
0
• Power supply using FA5541 is switching using self-excited oscillation.
• When IC turns the MOSFET ON ,drain current Id (primary current of T1) begins to rise
from zero.
• V(IS pin) is voltage-converted from the Id current.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 8
9. 2.Basic operation of switching power supply using FA5541
VG M1 turns ON M1 turns OFF
VDS and winding voltage
have step change
Vds
Id begins rising
Id reaches
reference level
Id
• When Id reaches the reference level, FA5541 will turn M1 OFF
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 9
10. 2.Basic operation of switching power supply using FA5541
IF(D1)
T1 D1
ON
M1
OFF +
OUT Cd
0 0 Vds
RZCD
ZCD
RS -
CZCD
K
0
REF
0
A
IS
0
FB
0
• When M1 turns OFF ,and the winding voltage of the transformers has step change
and IF(D1) is provided from the transformer into secondary side.
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11. 2.Basic operation of switching power supply using FA5541
IF(D1) IF(D1) is provided
from the transformer
into secondary side IF(D1) gets zero
Vsub drops
VSUB rapidly
V(ZCD) < Vth,
V(ZCD) Id begins rising M1 turns ON
Vth
• When IF(D1) gets zero, Vds drops rapidly due to resonance of transformers
inductance and Cd. At the same time Vsub also drops rapidly.
• When V(ZCD) < Vth(of valley detection) ,FA5541 turns M1 ON again
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 11
12. 3.Start-up sequence simulation
K K1
K_Linear C14
COUPLING = 1
L1 = Ls
4700pF
L2 = Lp
L3 = Lsub
C_T1
D21
2200pF
Y G865C15R
19V / 0 to 5A
L1
4.7uH
1 2 VO_19V
C2 2 1
R2
C1 56k 2200pF Ls D22
220uF Lp {Nsp*Nsp*Lp} Y G865C15R RL
V1 DBR1 {Lp} C4 3.84
D3SB80 9900uF C7
D1 3300uFx3 1000u
VAMPL = 141.42 DERA38-06 1 2
FREQ = 50
100V/50Hz M1
2SK3681-01S
Cd
220pF PARAMETERS: 0
D3 Np = 57 R7
D1NL20U_S 2k
10 R8 Ns = 10 R15 C10
R10 4.7k Nsub = 8 200k 0.01uF
FB
Lp = 360uH R6
10k
R1 Rsns Nsp = {Ns/Np}
7.5k 100 C8 R3
0.22 Nsubp = {Nsub/Np}
R11 2200pF 13k
D4
R14 PC1
100 D1NL20U_S 0 TLP281 C9
R13 R5 0.01uF
100k IS
K
10k
IC1
FA5541 R12 REF
ZCD D2
4.7 SR1
ZCD VH TA76432F R4
1
A
FB NC 15k
C13 DERA22-02
IS VCC Lsub
22pF FB
GND OUT
{Nsubp*Nsubp*Lp}
Auxiliary
SSIC = 0 2
C12 C11 C3
33u
winding
1000pF 4700pF
CVCC
0
No parasitic elements and no initial condition is set
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 12
13. 3.Start-up sequence simulation
VCC VSTOFF
VCCON ,VSTRST1
Auxiliary supply takes over
VCC pin stop charging current
OUT
FA5541 turn off FA5541 turn on
t1 t2 t3
Total start-up time
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 13
14. 3.Start-up sequence simulation
FA5541 under voltage lockout (UVLO) characteristics (VCC pin)
ON threshold voltage: VCCON = 10.2V
Startup circuit shutdown: VSTOFF = 12.4V
Startup circuit reset voltage: VSTRST1 = 10.2V
IC1
FA5541
ZCD VH
FB NC
R12
D2 I(Aux)
4.7
1
IS VCC
C2
GND OUT 33u DERA22-02
SSIC = 0
I(VCC) Lsub
{Nsubp*Nsubp*Lp}
2
0
t1,t2: VCC < VSTOFF ,startup circuit turns on ,VCC pin charges capacitor CVCC (C2).
t2: VCC reaches VCCON ,FA5541 is turned on
t3: after VCC reaches VSTOFF ,startup circuit turns off , VCC decreases until Auxiliary supply takes over.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 14
15. 3.Start-up sequence simulation
Design margin (CVCC=33uF)
Design margin (CVCC=22uF)
VSTRST1
CVCC=22uF
CVCC=33uF
VCC (CVCC=22uF)
Total start-up time (CVCC=33uF)
• the simulation result shows the tradeoff between Total start-up time and Design margin,
which is the difference of V(VCC) and VSTRST1 when the auxiliary winding takes
over from the IC startup circuit.
• 33uF-CVCC is selected for higher Design margin although total start-up time is high.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 15
16. 4.Bridge diode peak current at start-up
K K1
K_Linear C14
COUPLING = 1
L1 = Ls
4700pF
L2 = Lp
L3 = Lsub
C_T1
D21
2200pF
Y G865C15R
19V / 0 to 5A
L1
4.7uH
1 2 VO_19V
R2 C3 2 1
56k 2200pF
C1 Lp Ls D22
220uF {Lp} {Nsp*Nsp*Lp} Y G865C15R RL
V1 DBR1 C4 3.84
D3SB80 D1 9900uF C7
DERA38-06
1 2
3300uFx3 1000u
VAMPL = 141.42
FREQ = 50
100V/50Hz M1
2SK3681-01S
Cd
220pF PARAMETERS: 0
D3 Np = 57 R7
D1NL20U_S 2k
10 R8 Ns = 10 R15 C10
R10 4.7k Nsub = 8 200k 0.01uF
FB
Lp = 360uH R6
10k
R1 Rsns Nsp = {Ns/Np}
7.5k 100 C8 R3
0.22 Nsubp = {Nsub/Np}
R11 2200pF 13k
D4
R14 PC1
100 D1NL20U_S 0 TLP281 C9
R13 R5 0.01uF
100k IS
K
10k
IC1
FA5541 R12 REF
ZCD D2
4.7 SR1
ZCD VH TA76432F R4
1
Lsub A
FB NC 15k
{Nsubp*Nsubp*Lp}
C13 DERA22-02
IS VCC
22pF FB
GND OUT
SSIC = 0 2
C12 C11 C2
1000pF 4700pF {Cv cc} PARAMETERS:
CVCC = 33u
0
No parasitic elements and no initial condition is set
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 16
17. 4.Bridge diode peak current at start-up
I
• Simulation result of the current through bridge rectifier diode DBR1 when the power
supply is plug to the wall outlet. the peak current is approximately 9.8 which is less
than Absolute maximum value IFSM from the datasheet.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 17
20. 5.Transformer
• Lleak = LP(1-k2)
• LS/LP = N2
N : winding ratio of the transformer
VS = VP*(NS/NP)
VSUB = VP*(NSUB/NP)
• Transformer is modeled by using SPICE primitive k ,the transformer spec is Lp=360uH and
Np:Ns:Nsub=57:10:8
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22. 6.Transformer leakage inductance
M1: VDSS=600V
Design margin (Lleak=14.256uH) M1: VDS(t) (Zoom)
Design margin (Lleak=7.164uH)
• Transformer model using SPICE primitive k ,leakage inductance: Lleak = LP(1-k2)
• LP=360uH ,leakage inductance is14.256uH for k=0.98 and 7.164uH for k=0.99
• Check the VDS overshoot voltage versus the transformer leakage inductance.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 22
26. 8.Power MOSFET switching device
Peak
value
VDS(t) ID(t)
10usec. / Div.
Peak
value
VDS(t)
ID(t)
20msec. / Div.
• Simulation results shows the peak value of M1: VDS and ID .
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 26
27. 8.Power MOSFET switching device
M1 Power Loss
M1 Power Lossavg
10usec. / Div.
Peak
value
VDS(t) ID(t)
VGS(t)
• Simulation results shows the peak value of MOSFET VDS and ID . Calculated
switching power loss and average power loss are also shown
All Rights Reserved Copyright (C) Bee Technologies Corporation 2009 27