VLSI Presentation Part 2
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This document is part 2 of a presentation on a Tic Tac Toe VLSI project. It summarizes the layout aspects and overall implementation of the circuit, including the pitch, number of inputs and outputs, and transistor counts of each component. It also describes Verilog test code that was used to test the circuit and lists next steps of completing testing and layout.
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VLSI Presentation Part 2
- 1. Tic Tac Toe VLSI Project Presentation (Part 2) Aaron Williams and Shayda Shahbazi December 1, 2014
- 2. ● vdd/gnd ● clk 9 inputs (1 for each block) ● 18 outputs (9 for each player) ● 9 outputs (3 bits for counting win/loss/draw) ● 1 hidden input(1/2/3 for reset) Layout Aspects Overall Implementation ● Pitch = 35.4u ○ Due to High number of inputs per component
- 5. Transistor Count DFF: 6+4+8+8=26 transistors Memory: 26*18 + 8*18 + 6*9 + 12 = 678 Checker: 9*18 + 9*8 = 262 Comb: 9*6 = 54 Total Win:158*3 + 28 + 64*2 = 630 Turn: 164+10+16 = 190 Out of AI: 1814 Conditions: 6*9 +96+48=198 Filter: 10*9 + 18 = 108 Extra: 8*6 +4 +4+6+8+10+12+14+16 =122 Think: 4*10+4*8+6+18=96 Memory: 9*26 + 4 = 238 Memroy_Add:3*26 + 12+12+6+14+36=158 Win: 6*8 + 16 = 64 Counter:4*26 + 12 +14+ 34=164 Total AI: 198*2 +108*2+122+96+238+164=1232 3046 transistors total
- 10. Combination Win
- 11. Memory Main
- 12. Filter Component
- 13. Component Extra
- 14. Memory Add
- 16. Verilog Test Code -Tests applying a set of inputs to the circuit Future Tests: -Find a set of conditions that guarantee a Computer victory -Find a set of conditions that guarantee a Human victory -Find a set of conditions that guarantee a draw
- 17. Next Steps ● Complete testing ● Complete layout
- 18. Thank You!