Immediate assertions evaluate a boolean expression at a single point in time to check if a condition is true. Concurrent assertions describe behavior over time using a clock and can check for conditions over multiple clock cycles. Concurrent assertions use special operators like ## and [*] to specify delays between boolean expressions and check sequences of expressions in linear time. Useful SystemVerilog functions in concurrent assertions check for signal rises, falls, stability, past values, and sampling based on a clock.

1. SV assertion

2. • Immediate assertion
Need to write in procedural block as it is
evaluated at that time only. Boolean
expression is used.
example : HDR : assert (a==`DEFINE);
Simple to understand because same as if else
branch.

3. • Concurrent assertion
• Concurrent assertions describe behaviour that
spans over time. Unlike immediate assertions,
the evaluation model is based on a clock such
that a concurrent assertion is evaluated only
at the occurrence of a clock tick.
• It is based upon sequence of opertion over
span of time.

4. • A linear sequence is a finite list of
SystemVerilog Boolean expressions in a linear
order of increasing time.
• Special Operators for Concurrent assertions
• ## n : cycle delay
• [n1:n2] : range of cycle delay
• [*n1:n2] : consecutive repetition of one
sequence
• [-> n1 : n2] : goto operator nonconsecutive

5. • Useful functions :
• All below function uses clock given as arument
in sequence.
• $rose
• $fell
• $stable
• $past
• $sampled

6. • First match : first match is considered all
others are discarded.
• Throughout
• Within
• Property can be used in assume and cover
statements also.