1. Shubhra Singh
602, Durga Coral Appt. shubhrasingh98@gmail.com
Kadubeesanahalli Contact No.: +918861895903
Bangalore­560103
EMPLOYMENT
Samsung July 2014 to Present
Senior Software Engineer
➢ Contribution in optimizing clock driver framework of Exynos 7420. Gating unused clocks and
power optimization through efficient management of the mux, gate and divider clocks.
➢ Optimization of Legacy device drivers like PWM, ADC, Real Time Clock, Watchdog Timer for the
board bring up of Exynos 7880.
➢ Bug fixes in android kernel for OS upgradation projects
Nvidia Jan 2014 to June 2014
Software Engineer Intern
Project Tilte­Enhancement of Game­streaming Solutions using Speech Recognition
Using speech recognition to enhance user experience during game streaming. The speech recognition
technique is used in Nvidia’s GeForce Experience. Enhanced user experience by implementing voice
commands alongside previous hot key commands.
EDUCATION
B.Tech (ECE) from Indian Institute of Information Technology, Allahabad, India with CGPI of 8.8/10.00.
​Examination Institute SGPI/Percentage Session
Class XII (CBSE) DAV Public School, Patna 85.4% 2008­09
Class X (ICSE) Don Bosco Academy, Patna 95.5% 2006­07
AREA OF INTEREST
● Linux Kernel Programming
● Device Drivers
● Data Structures
● Basics of Operating System

2. SKILLS
● Kernel level programming of device drivers
● C, C++, Basic Python, MSDN, Verilog (HDL).
● Microprocessor 8086, Altium Nanoboard NB2 FPGA, Spartan 3e FPGA.
● Software Skills: Visual Studio, WinDbg, Eclipse, Perforce, MATLAB, Xilinx ISE Simulator.
COLLEGE PROJECTS
TITLE​: FPGA implementation of Data Encryption Standard (Cryptographic standard)
Duration​: 6 months; 7​th​
Semester
Technology used​: Verilog HDL
Description​: The aim is to encrypt a paragraph using DES algorithm in Verilog HDL, and decrypt the
paragraph back showing the result on PC transferred via UART.
Mentor​: Dr. Pramod Kumar (Assistant Professor)
TITLE​: Image Noise Reduction on Spartan 3E FPGA Using Verilog HDL
Duration​: 6 months; 6​th​
Semester
Technology used​: Verilog HDL, Open CV
Description​: Implemented the Algorithm for Adaptive Rank Order Filter to remove the impulse noise
i.e. salt and pepper noise from an image stored in the Block Ram. The output transferred
via UART and was integrated using Open CV.
Mentor​: Dr. Kusum Lata (Assistant Professor)
TITLE​: ​Gender Recognition using FIR Filter on Altium Nanoboard FPGA
Duration​: 6 months; 5​th​
Semester
Technology used​: Verilog HDL, C
Description​: The Speech after being amplified and digitized was filtered using FIR filter on the fpga.
The output from DAC was seen on CRO and also on the on­chip LED which glowed for
Male voice and remained off for female voice.
Mentor​: Dr. Ajit Singh (Lecturer)
TITLE​: ​2­digit Person Counter Using IR Sensors
Duration​: 6 months; 4​th​
Semester
Technology used​: PCB Designing, Soldering.
Description​: A 2­digit Up and Down counter was implemented on the PCB to count the number of
persons entering and leaving a room using IR Sensors having good range.
Mentor​: Dr. Rajat Singh (Assistant Professor)

3. Achievements:
● Was awarded ​Best Fresher​ in the System LSI Division of Samsung Bangalore.
● Secured ​8083​ rank in the general category in AIEEE 2010.
● Stood ​3​rd​
(95.5%) from my school in Class X Boards.
● Got 92%ile in Cyber Olympiad in Class 11​th​
.
● Took part in various quizzes, debate, and dance competitions in school.
Extra­curricular Achievements:
● Was the ​President of a Student Club ​(Dance Club) for one year, being responsible for organizing
various events and handling management issues.
● Volunteered for an NGO ‘Prayaas’ which worked in the area of primary education to
under­privileged children.
● Apart from all this my hobbies are reading novels, playing badminton, dancing and listening to
music.