This document provides an overview of sequential statements, loops, and other control structures in VHDL such as the for, while, next, exit, wait, null, and return statements. It includes examples of using these statements to implement counters, shift registers, and processes that wait for signals or time periods. The document also discusses functions and procedures in VHDL.

1. http://www.bized.co.uk
Session 9
Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud
Version 02 – October 2011
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2. http://www.bized.co.uk
9
-Sequential Statements
-Loops For-While
Contents -Next-Exit Statements
-Wait Statement
-Null Statement
-Assert Statement
-Functions
-Procedures
-Test Benches
-Dealing with Files
-Modelsim and Do Files
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Sequential
Statements
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Loop statement
Declaration
label : loop
Sequential statements contains the conditions to exit the loop
end loop label ;
Note that:
In order to exit from a loop an exit statement has to be used.
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Clock using loop
Clock : process(clk)
begin
L1: loop
clk <= not clk after 5 ns;
End loop L1;
End process;
Example
39
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Counter using Exit statement
L2 : loop
A := A+1;
Example
40
Exit L2 when A> 10;
End loop l2;
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While Loop statement
Declaration
while <condition> loop
Sequential statements;
end loop ;
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• Counter using while loop
While count < 10 loop
count <= count +1; Example
End loop;
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FOR Loop statement
Declaration
for <identifier> in range loop
Sequential statements;
end loop ;
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• 8 bit shift register
Example
42
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For i in 1 to 7 loop
reg (i-1) <= reg(i);
Shift Right
End loop;
7 6 5 4 3 2 1 0
Note : no need to define index “ i ”
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Next statement
A statement that may be used in a loop to cause the next iteration.
[ label: ] next [ label2 ] [ when condition ] ;
Example
next;
next outer_loop;
next when A>B;
next this_loop when C=D or done; -- done is a Boolean variable
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Exit statement
A statement that may be used in a loop to immediately exit the loop.
[ label: ] exit [ label2 ] [ when condition ] ;
Example
exit;
exit outer_loop;
exit when A>B;
exit this_loop when C=D or done; -- done is a Boolean variable
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Null statement
Used when a statement is needed but there is nothing to do.
[ label: ] null ;
Example
nothing : null;
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Return statement
Required statement in a function, optional in a procedure.
[ label: ] return [ expression ] ;
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Wait statement
The wait statement is a statement that causes suspension of a process or a procedure.
wait;
wait on signal_list;
wait until condition;
wait for time;
Important Notes
The wait statement can be located anywhere between begin and end process.
A process with a sensitivity list may not contain any wait statements.
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Examples on Wait Statement
Example 43
signal S1, S2 : Std_Logic;
...
process
begin
...
wait on S1, S2;
end process;
After executing all statements, the process will be suspended on the wait
statement and will be resumed when one of the S1 or S2 signals changes its
value.
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Examples on Wait Statement
Example 44
wait until Enable = '1';
-- this is equivalent to
-- loop
-- wait on Enable;
-- exit when Enable = '1';
-- end loop;
In this example, the wait statement will resume the process when the Enable
signal changes its value to '1'.
This is equivalent to the loop described in the comment below the first line. Please
note that the process is resumed on any change of the Enable signal. However, it
will awake the rest of the process only when the new value is '1'.
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Examples on Wait Statement
Example 45
wait for 50 ns;
A process containing this statement will be suspended for 50 ns.
Example 46
BIN_COMP : process
begin
wait on A, B until CLK = '1';
...
end process;
The process BIN_COMP is resumed after a change on either A or B signal, but
only when the value of the signal CLK is equal to '1'.
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Examples on Wait Statement
Example 47
G: process
begin
G0 <= '1' after 5 ns,
'0' after 10 ns,
'1' after 15 ns,
'0' after 20 ns;
G1 <= '1' after 5 ns,
'0' after 15 ns;
wait;
end process G;
In this process the values of signals G1 and G0 are set to '11', '10', '01', and '00'
at the time intervals 5, 10, 15 and 20 ns, respectively. When the wait statement
is encountered, the process is suspended forever.
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Subprograms : Functions and Procedures
Functions and procedures in VHDL, which are collectively known as subprograms, are
directly analogous to functions and procedures in a high-level software programming
language such as C or Pascal.
A procedure is a subprogram that has an argument list consisting of inputs and
outputs, and no return value.
A function is a subprogram that has only inputs in its argument list, and has a return
value.
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Functions
Declaration
function identifier [ ( formal parameter list ) ] return a_type is
begin
sequential statements
return some_value; -- of type a_type
end function identifier ;
Example
function random return float is
variable X : float;
begin
-- compute X
return X;
end function random ;
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Procedures
Declaration
procedure identifier [ ( formal parameter list ) ] is
declaration
begin
sequential statements
end procedure identifier ;
Example
procedure print_header is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, string'("A B C"));
writeline ( output, my_line );
end procedure print_header ;
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Test-Bench
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Test-Bench
Testbenches are used to test the design in a programmatic way
Testbench is used to:
Compare output responses against expected values
Test Bench Is my design
functioning
correctly?
Signal
generator UUT Osc.
Think as Hardware
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AND_GATE_TB
Example
48
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
Entity and_tb is
-- do we need ports here?
End entity; Testbench
--------------------------------------------
architecture waveform of and_tb is
Stimulus
component AND_gate generators AND
port (a : in std_logic;
b : in std_logic;
c : out std_logic);
end component;
signal x, y, z : std_logic;
Begin
x <= '0' ,
'1' after 40 ns;
y <= '0' ,
'1' after 20 ns,
'0' after 40 ns,
'1' after 60 ns;
uut : AND_gate PORT MAP ( a => x, b => y, c => z );
End architecture;
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Assertion
The ASSERT statement is a very useful statement for reporting textual strings
to the designer. The ASSERT statement checks the value of a boolean
expression for true or false. If the value is true, the statement does nothing. If
the value is false, the ASSERT statement outputs a userspecified text string to
the standard output to the terminal.
Assert statement
Check a Boolean condition
Report statement
Define a message that will be displayed when an error is found
Severity statement
Inform simulator how severe the situation is – form just a general note
to system failure
Think as Hardware
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Assertion
Think as Hardware
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Assertion
Think as Hardware
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• Counter Testbench
Example
49
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------
entity test is
port (clk, reset : in std_logic;
count : out std_logic_vector(3 downto 0));
end test;
--------------------------------------------
architecture Behavioral of test is
signal count_sig : std_logic_vector(3 downto 0) ;
begin
count <= count_sig;
---------------------
process(clk,reset)
begin if(reset='1') then
count_sig <=(others => '0');
elsif(clk'event and clk='1') then
count_sig <= count_sig +'1';
end if;
end process;
----------------------
end Behavioral;
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------
-- entity declaration for your testbench.
-- Dont declare any ports here
ENTITY test_tb IS
END test_tb;
---------------------------------------------------------------------------
ARCHITECTURE behavior OF test_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT test --'test' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such.
PORT(
clk : IN std_logic;
count : OUT std_logic_vector(3 downto 0);
reset : IN std_logic
);
END COMPONENT;
--------------------------------------------
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--------------------------------------------
--declare inputs and initialize them
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--------------------------------------------
--declare outputs and initialize them
signal count : std_logic_vector(3 downto 0);
--------------------------------------------
-- Clock period definitions
constant clk_period : time := 1 ns;
--------------------------------------------
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test PORT MAP (
clk => clk,
count => count,
reset => reset );
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-- Clock process definitions
-- clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
--------------------------------------------
-- Stimulus process
stim_proc: process
begin
wait for 7 ns;
reset <='1';
wait for 3 ns;
reset <='0';
wait for 17 ns;
reset <= '1';
wait for 1 ns;
reset <= '0';
wait;
end process;
END;
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• Reading from files
Example
50
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use STD.textio.all; --Dont forget to include this library for file operations.
ENTITY read_file IS
END read_file;
ARCHITECTURE tb OF read_file IS
signal bin_value : std_logic_vector(3 downto 0):="0000";
BEGIN
--Read process
process
file file_pointer : text;
variable line_num : line;
variable line_content : string(1 to 4);
variable char : character:='0';
begin
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file_open(file_pointer,"C:read.txt",READ_MODE);
--Open the file read.txt from the specified location for reading(READ_MODE).
while not endfile(file_pointer) loop --till the end of file is reached continue.
readline (file_pointer,line_num); --Read the whole line from the file
READ (line_num,line_content); --Read contents of the line from file into variable.
--For each character in the line convert it to binary value to store in bin_value
for j in 1 to 4 loop
char := line_content(j);
if(char = '0') then
bin_value(4-j) <= '0';
else
bin_value(4-j) <= '1';
end if;
end loop;
wait for 10 ns; --after reading each line wait for 10ns.
end loop;
file_close(file_pointer); --after reading all the lines close the file.
wait;
end process;
end tb;
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• Writing in files
Example
51
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
use STD.textio.all;
ENTITY write_file IS
END write_file;
ARCHITECTURE beha OF write_file IS
BEGIN
--Write process
process
file file_pointer : text;
variable line_content : string(1 to 4);
variable bin_value : std_logic_vector(3 downto 0);
variable line_num : line;
variable i,j : integer := 0;
variable char : character:='0';
begin
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--Open the file write.txt from the specified location for writing(WRITE_MODE).
file_open(file_pointer,"C:write.txt",WRITE_MODE);
--We want to store binary values from 0000 to 1111 in the file.
for i in 0 to 15 loop
bin_value := conv_std_logic_vector(i,4);
--convert each bit value to character for writing to file.
for j in 0 to 3 loop
if(bin_value(j) = '0') then
line_content(4-j) := '0';
else
line_content(4-j) := '1';
end if;
end loop;
write(line_num,line_content); --write the line.
writeline (file_pointer,line_num); --write the contents into the file.
wait for 10 ns; --wait for 10ns after writing the current line.
end loop;
file_close(file_pointer); --Close the file after writing.
wait;
end process;
end beha;
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• Do files using in Modelsim
Example
52
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1) Create a library for working in
vlib work
2) Compile your code
vcom -93 -explicit -work work filename.vhd #
3) Load it for simulation
vsim entityname
4) Open some selected windows for viewing view structure view signals
view wave #
5) Show some of the signals in the wave window
add wave -noupdate -divider Inputs
add wave –noupdate –color gold a
add wave -noupdate –color gold b
add wave -noupdate -divider Outputs
add wave -noupdate –color yellow c
6) Set some test patterns # a = 0, b = 0 at 0 ns
force a 0 0
force b 0 0
run 200 fs
# a = 1, b = 0 at 10 ns
force a 1 10
run 200 fs
# a = 0, b = 1 at 20 ns
force a 0 20
force b 1 20
run 200 fs
# a = 1, b = 1 at 30 ns
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Questions
Session-9
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Take Your Notes
Print the slides and take your notes here
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See You Next Session
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