The document is a two page curriculum vitae for Pavitra Sharath. It includes her personal information and contact details, her education history with a bachelor's degree in electronics and communication engineering from 2014, her skills including languages known and technical skills, and an example project in image compression using fractal coding.

1. Curriculum Vitae Pavitra Sharath
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PERSONAL INFORMATION Ms.Pavitra Sharath
13/1,Schatzdorfer Straße, Ried Im Innkreis, 4910, Österreich
0043-06604049988
pavitratm@gmail.com
Sex Female | Date of birth 24/01/1992 | Nationality Indian
EDUCATIONAND TRAINING
PERSONAL SKILLS
Seeking a challenging career with a progressive organization that provides an opportunity to capitalize
my Technical skills & abilities in field of Electronics and communication Engineering to become a
professional of excellent repute by effectively contributing towards the goal of Organization.
July 2010-July2014 Bachelors of Engineering in Electronics and Communication
GSSS Institute of Engineering and Technology For Women Mysore, India
University of Visvesvaraya technology Belgaum, Karnataka
▪ Linear IC’S and applications
▪ Embedded system design
▪ Computer communication network
▪ Microelectronics circuits
▪ Logic design
▪ Campus connect training program conducted by Infosys and Career Prime
Communication skills ▪ Highly motivated and eager to learn new things.
▪ Strong motivational and leadership skills.
▪ Excellent communication skills in written and verbal both
▪ Ability to work as individual as well as in group.
Mother tongue Kannada, English
Job-related skills ▪ Expert in implementation of each step of project.
▪ Eager to learn new technologies and methodologies.
▪ Always willing to innovate the new things which can improve the existing technology.

2. Curriculum Vitae Pavitra Sharath
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Drawing, Reading books.
ADDITIONAL INFORMATION
ANNEXES
Computer skills
▪ Good command of Microsoft Office tools.
▪ Basic C, HDL.
▪ Micro controller and processor.
Other skills
Projects ▪ PROJECT NAME :Application to Image compression using fractal coding in Cadence
▪ PROJECT DESCRIPTION: Project involves in designing the fractal encoder in HDL platform and
simulating it in cadence incisive simulator, the time consumed is found to be less, memory occupied
has reduced and idea behind the project is to storing images in less memory leads to a direct
reduction in storage cost and fast data transmissions. Fractal image compression is well suited for
applications requiring fast access to high quality images.
▪ LOCATION : Bangalore
▪ COMPANY : NXG Semiconductor Technologies
▪ copies of degrees and qualifications