This document contains the results of students who took exams in April/May 2012 for various subjects in M Tech programs at Jawaharlal Nehru Technological University Anantapur. It lists the student ID, subject codes and names, internal marks, external marks, total marks and results for multiple students. The results range from passes to fails for different subjects.
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
M.tech i sem results
1. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
09F61D5717 SILPA V
9D57102 ANALOG IC DESIGN 27 43 70 P
10F61D5707 CHAKRAVARTHI MOHAN
9D57102 ANALOG IC DESIGN 36 5 41 F
9D57106a EMBEDDED SYSTEM CONCEPTS 39 15 54 F
11F61D0401 BHARAT KUMAR K
9D04102 FINITE ELEMENT METHODS 40 42 82 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 38 38 76 P
9D04104 GEOMETRIC MODELING 38 50 88 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 36 40 76 P
9D04106b COMPUTER AIDED PROCESS PLANNING 39 42 81 P
9D04107 MODELLING AND CNC LAB 40 59 99 P
9DBS101 COMPUTATIONAL METHODS 40 45 85 P
11F61D0402 BINDUMADHAVI B
9D04102 FINITE ELEMENT METHODS 39 36 75 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 39 38 77 P
9D04104 GEOMETRIC MODELING 38 38 76 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 28 30 58 P
9D04106b COMPUTER AIDED PROCESS PLANNING 35 40 75 P
9D04107 MODELLING AND CNC LAB 39 58 97 P
9DBS101 COMPUTATIONAL METHODS 38 33 71 P
11F61D0403 GNANAPRAKASH V
9D04102 FINITE ELEMENT METHODS 34 28 62 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 36 34 70 P
9D04104 GEOMETRIC MODELING 36 32 68 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 31 28 59 P
9D04106b COMPUTER AIDED PROCESS PLANNING 38 44 82 P
9D04107 MODELLING AND CNC LAB 38 56 94 P
9DBS101 COMPUTATIONAL METHODS 24 24 48 F
11F61D0404 HARI HARAN VUPPALA
9D04102 FINITE ELEMENT METHODS 39 42 81 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 39 34 73 P
9D04104 GEOMETRIC MODELING 38 40 78 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 30 33 63 P
9D04106b COMPUTER AIDED PROCESS PLANNING 39 42 81 P
9D04107 MODELLING AND CNC LAB 37 57 94 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 1 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
2. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9DBS101 COMPUTATIONAL METHODS 36 30 66 P
11F61D0405 JAYA KISHORE S
9D04102 FINITE ELEMENT METHODS 38 37 75 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 38 26 64 P
9D04104 GEOMETRIC MODELING 39 30 69 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 39 38 77 P
9D04106b COMPUTER AIDED PROCESS PLANNING 40 44 84 P
9D04107 MODELLING AND CNC LAB 39 58 97 P
9DBS101 COMPUTATIONAL METHODS 40 26 66 P
11F61D0406 PALAMANGALAM RAMESH
9D04102 FINITE ELEMENT METHODS 40 40 80 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 40 30 70 P
9D04104 GEOMETRIC MODELING 38 32 70 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 32 26 58 P
9D04106b COMPUTER AIDED PROCESS PLANNING 40 44 84 P
9D04107 MODELLING AND CNC LAB 39 59 98 P
9DBS101 COMPUTATIONAL METHODS 39 33 72 P
11F61D0407 SOWJANYA KUNTRAPAKAM
9D04102 FINITE ELEMENT METHODS 40 46 86 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 40 32 72 P
9D04104 GEOMETRIC MODELING 38 34 72 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 32 34 66 P
9D04106b COMPUTER AIDED PROCESS PLANNING 39 36 75 P
9D04107 MODELLING AND CNC LAB 38 58 96 P
9DBS101 COMPUTATIONAL METHODS 40 35 75 P
11F61D0408 SREEDHAR N
9D04102 FINITE ELEMENT METHODS 38 34 72 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 38 44 82 P
9D04104 GEOMETRIC MODELING 39 28 67 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 35 29 64 P
9D04106b COMPUTER AIDED PROCESS PLANNING 39 30 69 P
9D04107 MODELLING AND CNC LAB 39 58 97 P
9DBS101 COMPUTATIONAL METHODS 34 28 62 P
11F61D0409 I SRINIVASA REDDY
9D04102 FINITE ELEMENT METHODS 36 49 85 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 34 14 48 F
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 2 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
3. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D04104 GEOMETRIC MODELING 32 38 70 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 28 30 58 P
9D04106b COMPUTER AIDED PROCESS PLANNING 34 26 60 P
9D04107 MODELLING AND CNC LAB 36 50 86 P
9DBS101 COMPUTATIONAL METHODS 31 38 69 P
11F61D0410 SRINIVASAN MV
9D04102 FINITE ELEMENT METHODS 34 27 61 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 39 36 75 P
9D04104 GEOMETRIC MODELING 36 26 62 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 31 32 63 P
9D04106b COMPUTER AIDED PROCESS PLANNING 38 34 72 P
9D04107 MODELLING AND CNC LAB 38 58 96 P
9DBS101 COMPUTATIONAL METHODS 31 27 58 P
11F61D0411 AKULA SURESH
9D04102 FINITE ELEMENT METHODS 36 34 70 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 36 34 70 P
9D04104 GEOMETRIC MODELING 36 24 60 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 28 20 48 F
9D04106b COMPUTER AIDED PROCESS PLANNING 32 30 62 P
9D04107 MODELLING AND CNC LAB 38 57 95 P
9DBS101 COMPUTATIONAL METHODS 32 34 66 P
11F61D0412 BELLAM SWATHI
9D04102 FINITE ELEMENT METHODS 32 30 62 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 38 30 68 P
9D04104 GEOMETRIC MODELING 38 24 62 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 25 26 51 P
9D04106b COMPUTER AIDED PROCESS PLANNING 38 30 68 P
9D04107 MODELLING AND CNC LAB 37 55 92 P
9DBS101 COMPUTATIONAL METHODS 31 28 59 P
11F61D0413 B VIJAYAKUMAR
9D04102 FINITE ELEMENT METHODS 38 40 78 P
9D04103 COMPUTER INTEGRATED MANUFACTURING 36 40 76 P
9D04104 GEOMETRIC MODELING 36 34 70 P
9D04105 ADVANCE IN MANUFACTURING TECHNOLOGY 30 36 66 P
9D04106b COMPUTER AIDED PROCESS PLANNING 35 38 73 P
9D04107 MODELLING AND CNC LAB 36 56 92 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 3 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
4. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9DBS101 COMPUTATIONAL METHODS 35 35 70 P
11F61D5401 AJITH KUMAR DEENADAYAL
9D49101 MODERN CONTROL THEORY 35 24 59 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 38 24 62 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 32 34 66 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 39 52 91 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 31 43 74 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 36 51 87 P
9D54107 POWER CONVERTERS LAB 35 51 86 P
11F61D5402 SANALA BHANUPRAKASH
9D49101 MODERN CONTROL THEORY 34 32 66 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 36 25 61 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 35 25 60 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 36 41 77 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 31 21 52 F
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 35 46 81 P
9D54107 POWER CONVERTERS LAB 35 51 86 P
11F61D5403 JAGADEESH P V
9D49101 MODERN CONTROL THEORY 40 48 88 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 39 33 72 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 38 37 75 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 39 54 93 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 40 44 84 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 40 53 93 P
9D54107 POWER CONVERTERS LAB 40 58 98 P
11F61D5404 JAYAVELU M K
9D49101 MODERN CONTROL THEORY 38 29 67 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 40 40 80 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 39 46 85 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 39 49 88 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 40 49 89 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 33 52 85 P
9D54107 POWER CONVERTERS LAB 38 58 96 P
11F61D5406 P MODINI
9D49101 MODERN CONTROL THEORY 39 18 57 F
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 40 34 74 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 4 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
5. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 35 38 73 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 38 40 78 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 35 43 78 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 39 46 85 P
9D54107 POWER CONVERTERS LAB 39 55 94 P
11F61D5407 MURALI KRISHNA N
9D49101 MODERN CONTROL THEORY 33 21 54 F
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 36 30 66 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 28 29 57 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 38 46 84 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 34 38 72 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 32 50 82 P
9D54107 POWER CONVERTERS LAB 37 54 91 P
11F61D5408 P A PRABHAKARA
9D49101 MODERN CONTROL THEORY 40 29 69 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 38 39 77 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 33 37 70 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 35 46 81 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 35 37 72 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 37 49 86 P
9D54107 POWER CONVERTERS LAB 37 54 91 P
11F61D5409 VEMPALLI PRASAD RAJU
9D49101 MODERN CONTROL THEORY 40 45 85 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 40 39 79 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 30 35 65 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 39 45 84 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 34 48 82 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 39 49 88 P
9D54107 POWER CONVERTERS LAB 38 56 94 P
11F61D5410 PUSHPA N
9D49101 MODERN CONTROL THEORY 40 44 84 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 40 48 88 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 38 46 84 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 40 51 91 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 40 49 89 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 39 53 92 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 5 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
6. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D54107 POWER CONVERTERS LAB 40 58 98 P
11F61D5411 RAJASEKHAR A
9D49101 MODERN CONTROL THEORY 31 25 56 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 35 34 69 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 32 33 65 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 27 36 63 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 24 41 65 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 28 49 77 P
9D54107 POWER CONVERTERS LAB 37 57 94 P
11F61D5412 REDDIPRASANNA ANDE
9D49101 MODERN CONTROL THEORY 40 44 84 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 38 45 83 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 39 40 79 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 40 51 91 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 40 50 90 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 37 48 85 P
9D54107 POWER CONVERTERS LAB 40 58 98 P
11F61D5413 SABARINATH G
9D49101 MODERN CONTROL THEORY 30 21 51 F
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 35 36 71 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 35 30 65 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 34 33 67 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 35 38 73 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 36 46 82 P
9D54107 POWER CONVERTERS LAB 38 56 94 P
11F61D5414 SREENIVASULU REDDY M
9D49101 MODERN CONTROL THEORY 40 19 59 F
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 36 32 68 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 36 35 71 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 38 50 88 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 34 47 81 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 36 52 88 P
9D54107 POWER CONVERTERS LAB 39 56 95 P
11F61D5415 BANDI SWAMIKONDA
9D49101 MODERN CONTROL THEORY 40 42 82 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 38 46 84 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 6 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
7. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 36 41 77 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 36 45 81 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 34 49 83 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 33 50 83 P
9D54107 POWER CONVERTERS LAB 37 55 92 P
11F61D5416 VIJAYA LAKSHMI K
9D49101 MODERN CONTROL THEORY 36 41 77 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 35 30 65 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 35 29 64 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 34 48 82 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 36 48 84 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 37 50 87 P
9D54107 POWER CONVERTERS LAB 38 56 94 P
11F61D5417 K YAMINI
9D49101 MODERN CONTROL THEORY 40 43 83 P
9D49102 MICROPROCESSORS AND MICROCONTROLLERS 39 45 84 P
9D49106 NEURAL NETWORKS AND FUZZY SYSTEMS 39 43 82 P
9D54103 PRINCIPLES OF MACHINE MODELLING ANALYSIS] 38 50 88 P
9D54104 ANALYSIS OF POWER ELECTRONIC CONVERTERS 40 50 90 P
9D54105 POWER ELECTRONIC CONTROL OF DC DRIVES 35 47 82 P
9D54107 POWER CONVERTERS LAB 40 58 98 P
11F61D5501 PANDIGUNTA ARUNA KUMARI
9D06102 EMBEDDED SYSTEM CONCEPTS 34 31 65 P
9D06103 ADVANCED COMPUTER ARCHITECTURE 38 28 66 P
9D55101 ADVANCED DSP & APPLICATIONS 39 26 65 P
9D55104 MICRO CONTROLLERS & INTERFACING 38 31 69 P
9D55105 OPERTING SYSTEMS 38 24 62 P
9D55107 MICROCONTROLLERS & INTERFACING LAB 36 55 91 P
9D57101 VLSI TECHNOLOGY 38 35 73 P
11F61D5502 B M R MANASA
9D06102 EMBEDDED SYSTEM CONCEPTS 40 38 78 P
9D06103 ADVANCED COMPUTER ARCHITECTURE 38 38 76 P
9D55101 ADVANCED DSP & APPLICATIONS 38 34 72 P
9D55104 MICRO CONTROLLERS & INTERFACING 38 45 83 P
9D55105 OPERTING SYSTEMS 38 31 69 P
9D55107 MICROCONTROLLERS & INTERFACING LAB 36 57 93 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 7 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
8. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D57101 VLSI TECHNOLOGY 38 45 83 P
11F61D5503 M S NIRANJANI
9D06102 EMBEDDED SYSTEM CONCEPTS 36 36 72 P
9D06103 ADVANCED COMPUTER ARCHITECTURE 36 36 72 P
9D55101 ADVANCED DSP & APPLICATIONS 30 37 67 P
9D55104 MICRO CONTROLLERS & INTERFACING 38 35 73 P
9D55105 OPERTING SYSTEMS 40 35 75 P
9D55107 MICROCONTROLLERS & INTERFACING LAB 37 55 92 P
9D57101 VLSI TECHNOLOGY 38 37 75 P
11F61D5504 PAVAN KUMAR GANDLA
9D06102 EMBEDDED SYSTEM CONCEPTS 40 38 78 P
9D06103 ADVANCED COMPUTER ARCHITECTURE 39 40 79 P
9D55101 ADVANCED DSP & APPLICATIONS 35 34 69 P
9D55104 MICRO CONTROLLERS & INTERFACING 39 41 80 P
9D55105 OPERTING SYSTEMS 39 28 67 P
9D55107 MICROCONTROLLERS & INTERFACING LAB 38 56 94 P
9D57101 VLSI TECHNOLOGY 35 40 75 P
11F61D5505 G VINODKUMAR
9D06102 EMBEDDED SYSTEM CONCEPTS 38 32 70 P
9D06103 ADVANCED COMPUTER ARCHITECTURE 37 26 63 P
9D55101 ADVANCED DSP & APPLICATIONS 35 26 61 P
9D55104 MICRO CONTROLLERS & INTERFACING 39 32 71 P
9D55105 OPERTING SYSTEMS 40 27 67 P
9D55107 MICROCONTROLLERS & INTERFACING LAB 39 58 97 P
9D57101 VLSI TECHNOLOGY 36 25 61 P
11F61D5701 M JANARDHANA
9D57101 VLSI TECHNOLOGY 23 26 49 F
9D57102 ANALOG IC DESIGN 0 7 7 F
9D57103 DIGITAL IC DESIGN 0 AB 0 F
9D57104 HARDWARE DESCRIPTION LANGUAGES 27 AB 27 F
9D57105 HARDWARE SOFTWARE CO-DESIGN 0 AB 0 F
9D57106 EMBEDDED SYSTEM CONCEPTS 0 AB 0 F
9D57107 DIGITAL IC DESIGN LAB 36 51 87 P
11F61D5702 MANI MOHAN P
9D57101 VLSI TECHNOLOGY 30 28 58 P
9D57102 ANALOG IC DESIGN 38 30 68 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 8 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
9. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D57103 DIGITAL IC DESIGN 38 31 69 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 37 43 80 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 38 24 62 P
9D57106a EMBEDDED SYSTEM CONCEPTS 39 29 68 P
9D57107 DIGITAL IC DESIGN LAB 39 59 98 P
11F61D5703 P MOHANAMMA
9D57101 VLSI TECHNOLOGY 38 44 82 P
9D57102 ANALOG IC DESIGN 35 35 70 P
9D57103 DIGITAL IC DESIGN 38 53 91 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 35 54 89 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 40 33 73 P
9D57106a EMBEDDED SYSTEM CONCEPTS 38 43 81 P
9D57107 DIGITAL IC DESIGN LAB 38 60 98 P
11F61D5704 MYTHILI P G S
9D57101 VLSI TECHNOLOGY 39 45 84 P
9D57102 ANALOG IC DESIGN 38 36 74 P
9D57103 DIGITAL IC DESIGN 40 49 89 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 36 48 84 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 40 33 73 P
9D57106a EMBEDDED SYSTEM CONCEPTS 38 43 81 P
9D57107 DIGITAL IC DESIGN LAB 38 59 97 P
11F61D5705 EARLA NAGARAJU
9D57101 VLSI TECHNOLOGY 36 30 66 P
9D57102 ANALOG IC DESIGN 26 24 50 P
9D57103 DIGITAL IC DESIGN 35 27 62 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 30 29 59 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 36 24 60 P
9D57106a EMBEDDED SYSTEM CONCEPTS 32 28 60 P
9D57107 DIGITAL IC DESIGN LAB 38 55 93 P
11F61D5706 NITHYAVEL KRISHNA A
9D57101 VLSI TECHNOLOGY 35 27 62 P
9D57102 ANALOG IC DESIGN 30 24 54 P
9D57103 DIGITAL IC DESIGN 31 30 61 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 30 30 60 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 38 26 64 P
9D57106a EMBEDDED SYSTEM CONCEPTS 32 7 39 F
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 9 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
10. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D57107 DIGITAL IC DESIGN LAB 37 56 93 P
11F61D5707 THOTI PARDHASARATHY
9D57101 VLSI TECHNOLOGY 24 24 48 F
9D57102 ANALOG IC DESIGN 28 14 42 F
9D57103 DIGITAL IC DESIGN 30 24 54 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 26 35 61 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 33 24 57 P
9D57106a EMBEDDED SYSTEM CONCEPTS 20 16 36 F
9D57107 DIGITAL IC DESIGN LAB 36 44 80 P
11F61D5708 BETHANAMUDI PAVAN KALYAN
9D57101 VLSI TECHNOLOGY 38 26 64 P
9D57102 ANALOG IC DESIGN 30 27 57 P
9D57103 DIGITAL IC DESIGN 34 33 67 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 30 26 56 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 37 24 61 P
9D57106a EMBEDDED SYSTEM CONCEPTS 34 28 62 P
9D57107 DIGITAL IC DESIGN LAB 38 58 96 P
11F61D5709 M SATHISHKUMAR
9D57101 VLSI TECHNOLOGY 34 32 66 P
9D57102 ANALOG IC DESIGN 30 26 56 P
9D57103 DIGITAL IC DESIGN 34 31 65 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 30 34 64 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 40 24 64 P
9D57106a EMBEDDED SYSTEM CONCEPTS 24 17 41 F
9D57107 DIGITAL IC DESIGN LAB 39 57 96 P
11F61D5710 R SEELANAND KUMAR
9D57101 VLSI TECHNOLOGY 35 27 62 P
9D57102 ANALOG IC DESIGN 27 19 46 F
9D57103 DIGITAL IC DESIGN 30 24 54 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 30 28 58 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 38 24 62 P
9D57106a EMBEDDED SYSTEM CONCEPTS 34 25 59 P
9D57107 DIGITAL IC DESIGN LAB 36 60 96 P
11F61D5711 DUVVURU SINDHU
9D57101 VLSI TECHNOLOGY 38 29 67 P
9D57102 ANALOG IC DESIGN 38 30 68 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 10 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
11. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D57103 DIGITAL IC DESIGN 38 43 81 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 37 31 68 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 39 30 69 P
9D57106a EMBEDDED SYSTEM CONCEPTS 36 24 60 P
9D57107 DIGITAL IC DESIGN LAB 38 58 96 P
11F61D5712 SUMA LATHA S
9D57101 VLSI TECHNOLOGY 38 35 73 P
9D57102 ANALOG IC DESIGN 39 29 68 P
9D57103 DIGITAL IC DESIGN 38 42 80 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 37 43 80 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 39 28 67 P
9D57106a EMBEDDED SYSTEM CONCEPTS 36 33 69 P
9D57107 DIGITAL IC DESIGN LAB 39 60 99 P
11F61D5713 THEJASREE VARDHI
9D57101 VLSI TECHNOLOGY 35 38 73 P
9D57102 ANALOG IC DESIGN 39 40 79 P
9D57103 DIGITAL IC DESIGN 38 47 85 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 35 49 84 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 40 29 69 P
9D57106a EMBEDDED SYSTEM CONCEPTS 38 38 76 P
9D57107 DIGITAL IC DESIGN LAB 40 59 99 P
11F61D5714 VENU ALLAPAKAM
9D57101 VLSI TECHNOLOGY 32 35 67 P
9D57102 ANALOG IC DESIGN 32 35 67 P
9D57103 DIGITAL IC DESIGN 38 40 78 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 34 41 75 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 38 30 68 P
9D57106a EMBEDDED SYSTEM CONCEPTS 38 32 70 P
9D57107 DIGITAL IC DESIGN LAB 38 58 96 P
11F61D5715 VIJAY KUMAR D
9D57101 VLSI TECHNOLOGY 39 30 69 P
9D57102 ANALOG IC DESIGN 32 27 59 P
9D57103 DIGITAL IC DESIGN 38 34 72 P
9D57104 HARDWARE DESCRIPTION LANGUAGES 34 43 77 P
9D57105 HARDWARE SOFTWARE CO-DESIGN 37 25 62 P
9D57106a EMBEDDED SYSTEM CONCEPTS 31 26 57 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 11 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
12. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D57107 DIGITAL IC DESIGN LAB 39 58 97 P
11F61D5801 S CHANBASHA
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 35 31 66 P
9D58102 DISCRETE STRUCTURES 35 25 60 P
9D58103 COMPUTER SYSTEMS DESIGN 34 24 58 P
9D58104 JAVA AND WEB TECHNOLOGIES 27 33 60 P
9D58105 SOFTWARE ENGINEERING 35 30 65 P
9D58106 DISTRIBUTED DATABASES 32 2 34 F
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 35 52 87 P
11F61D5802 M CHENCHULAKSHMI
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 40 46 86 P
9D58102 DISCRETE STRUCTURES 40 38 78 P
9D58103 COMPUTER SYSTEMS DESIGN 40 30 70 P
9D58104 JAVA AND WEB TECHNOLOGIES 40 56 96 P
9D58105 SOFTWARE ENGINEERING 39 31 70 P
9D58106 DISTRIBUTED DATABASES 40 25 65 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 40 59 99 P
11F61D5803 P C DEVI
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 40 45 85 P
9D58102 DISCRETE STRUCTURES 40 25 65 P
9D58103 COMPUTER SYSTEMS DESIGN 40 28 68 P
9D58104 JAVA AND WEB TECHNOLOGIES 38 55 93 P
9D58105 SOFTWARE ENGINEERING 39 36 75 P
9D58106 DISTRIBUTED DATABASES 40 30 70 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 40 57 97 P
11F61D5804 DIVYAJA P
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 40 39 79 P
9D58102 DISCRETE STRUCTURES 39 28 67 P
9D58103 COMPUTER SYSTEMS DESIGN 39 34 73 P
9D58104 JAVA AND WEB TECHNOLOGIES 40 49 89 P
9D58105 SOFTWARE ENGINEERING 36 33 69 P
9D58106 DISTRIBUTED DATABASES 39 22 61 F
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 40 59 99 P
11F61D5805 HARI KRISHNA THAMBI
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 35 33 68 P
9D58102 DISCRETE STRUCTURES 36 21 57 F
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 12 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
13. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D58103 COMPUTER SYSTEMS DESIGN 32 28 60 P
9D58104 JAVA AND WEB TECHNOLOGIES 35 34 69 P
9D58105 SOFTWARE ENGINEERING 34 33 67 P
9D58106 DISTRIBUTED DATABASES 32 23 55 F
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 39 57 96 P
11F61D5806 SINGAREDDY HEMASRI
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 38 44 82 P
9D58102 DISCRETE STRUCTURES 37 26 63 P
9D58103 COMPUTER SYSTEMS DESIGN 40 35 75 P
9D58104 JAVA AND WEB TECHNOLOGIES 35 51 86 P
9D58105 SOFTWARE ENGINEERING 39 28 67 P
9D58106 DISTRIBUTED DATABASES 40 35 75 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 38 56 94 P
11F61D5807 KALYANI KURAGAYALA
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 38 32 70 P
9D58102 DISCRETE STRUCTURES 40 15 55 F
9D58103 COMPUTER SYSTEMS DESIGN 34 25 59 P
9D58104 JAVA AND WEB TECHNOLOGIES 38 38 76 P
9D58105 SOFTWARE ENGINEERING 34 26 60 P
9D58106 DISTRIBUTED DATABASES 39 21 60 F
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 39 56 95 P
11F61D5808 KARTHIK KUMAR B
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 38 31 69 P
9D58102 DISCRETE STRUCTURES 39 28 67 P
9D58103 COMPUTER SYSTEMS DESIGN 32 25 57 P
9D58104 JAVA AND WEB TECHNOLOGIES 38 29 67 P
9D58105 SOFTWARE ENGINEERING 36 34 70 P
9D58106 DISTRIBUTED DATABASES 35 23 58 F
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 38 55 93 P
11F61D5809 M LOKESH
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 38 37 75 P
9D58102 DISCRETE STRUCTURES 40 24 64 P
9D58103 COMPUTER SYSTEMS DESIGN 36 34 70 P
9D58104 JAVA AND WEB TECHNOLOGIES 40 40 80 P
9D58105 SOFTWARE ENGINEERING 36 31 67 P
9D58106 DISTRIBUTED DATABASES 34 27 61 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 13 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
14. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 39 57 96 P
11F61D5810 SANGI NARASIMHULU
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 35 35 70 P
9D58102 DISCRETE STRUCTURES 39 36 75 P
9D58103 COMPUTER SYSTEMS DESIGN 34 30 64 P
9D58104 JAVA AND WEB TECHNOLOGIES 38 36 74 P
9D58105 SOFTWARE ENGINEERING 36 31 67 P
9D58106 DISTRIBUTED DATABASES 32 31 63 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 37 54 91 P
11F61D5811 R PADMINI
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 40 43 83 P
9D58102 DISCRETE STRUCTURES 40 35 75 P
9D58103 COMPUTER SYSTEMS DESIGN 39 28 67 P
9D58104 JAVA AND WEB TECHNOLOGIES 40 50 90 P
9D58105 SOFTWARE ENGINEERING 38 32 70 P
9D58106 DISTRIBUTED DATABASES 38 33 71 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 40 59 99 P
11F61D5812 MADDELA PRAVEEN KUMAR
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 38 41 79 P
9D58102 DISCRETE STRUCTURES 40 33 73 P
9D58103 COMPUTER SYSTEMS DESIGN 36 39 75 P
9D58104 JAVA AND WEB TECHNOLOGIES 36 46 82 P
9D58105 SOFTWARE ENGINEERING 35 29 64 P
9D58106 DISTRIBUTED DATABASES 38 33 71 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 39 55 94 P
11F61D5813 PRIYADARSHINI R
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 38 40 78 P
9D58102 DISCRETE STRUCTURES 40 27 67 P
9D58103 COMPUTER SYSTEMS DESIGN 38 37 75 P
9D58104 JAVA AND WEB TECHNOLOGIES 40 36 76 P
9D58105 SOFTWARE ENGINEERING 35 33 68 P
9D58106 DISTRIBUTED DATABASES 40 30 70 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 40 58 98 P
11F61D5815 SUSHMA C
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 35 31 66 P
9D58102 DISCRETE STRUCTURES 39 19 58 F
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 14 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date
15. JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
ANANTAPUR - 515 002(A. P.) INDIA
EXAMINATION BRANCH
M Tech I Semester Regular and Supplementary Examinations - April/May 2012 Results
-------------------------------------------------------------------------------------------------------------------------------------------------
SUBCODE SUB NAME I.M E.M TOTAL RESULT
-------------------------------------------------------------------------------------------------------------------------------------------------
9D58103 COMPUTER SYSTEMS DESIGN 28 24 52 P
9D58104 JAVA AND WEB TECHNOLOGIES 35 43 78 P
9D58105 SOFTWARE ENGINEERING 38 26 64 P
9D58106 DISTRIBUTED DATABASES 32 31 63 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 38 53 91 P
11F61D5816 SWETHA S R
9D58101 ADVANCED DATA STRUCTURES AND ALGORITHMS 38 36 74 P
9D58102 DISCRETE STRUCTURES 39 24 63 P
9D58103 COMPUTER SYSTEMS DESIGN 39 34 73 P
9D58104 JAVA AND WEB TECHNOLOGIES 35 49 84 P
9D58105 SOFTWARE ENGINEERING 39 33 72 P
9D58106 DISTRIBUTED DATABASES 35 33 68 P
9D58107 SOFTWARE LAB-I (COVERING THE EXPERIMENTS:DATA STRUCTURES & 38 55 93 P
CONTROLLER OF EXAMINATIONS i/c
Monday, July 09, 2012 Page 15 of 15
Note: Any discrepancy in the result noted above must be brought to the notice of the Controller of Examinations, within two
weeks from the above date