this is chapter 7 of computer architecture and organization which is reduced instruction set computer .

1. Department of Electrical and Computer Engineering
Chapter 7: Reduced Instruction Set
Computers
Computer Architecture
and Organization

2. Major Advances in Computers
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Computer Architecture and Organization
• Since the development of the stored-program computer
around 1950, major advance in computer
• The family concept
• IBM System/360 1964
• The difference in price and performance due to the difference
implementation of the same architecture.
• Same architecture but different implementation.
• Micro programmed control unit
• Idea by Wilkes 1951
• Produced by IBM S/360 1964
• Cache memory
• IBM S/360 model 85 1969
• The insertion of this element into memory hierarchy dramatically
improves performance.

3. Major Advances in Computers …
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Computer Architecture and Organization
• Solid State RAM
• Microprocessors
• Intel 4004 1971
• Pipelining
• Introduces parallelism into fetch execute cycle
• Multiple processors

4. The Next Step - RISC
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Computer Architecture and Organization
• Reduced Instruction Set Computer
• Key features
• Large number of general purpose registers
• Use of compiler technology to optimize register use
• Limited and simple instruction set
• Emphasis on optimising the instruction pipeline

5. Comparison of processors
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Computer Architecture and Organization

6. Driving force for CISC
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Computer Architecture and Organization
• Software costs far exceed hardware costs.
• Programs continues to exhibit new bugs after year of
operation.
• The response from researchers and industries has been
to develop.
• Increasingly complex high level languages
• To taker of much of the detail
• Unfortunately, this solution give rise another problem.
• Semantic gap – the difference between the operations provides
in HLLs and those provided in computer architecture.
• Designers responded with architecture to close this gap.

7. Driving force for CISC
• Leads to:
• Large instruction sets
• More addressing modes
• Hardware implementations of HLL statements
• e.g. CASE (switch) machine instruction on VAX
(a computer by DEC)
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8. Intention of CISC
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Computer Architecture and Organization
• Ease compiler writing
• Improve execution efficiency
• Complex operations can be implemented in microcode
• Support more complex HLLs

9. Execution Characteristics
• Meanwhile, a number of studies have been done over the
years to determine the characteristics and pattern of
execution of machine instructions.
• Such studies result a different approach.
• To make the architecture that support HLL simpler rather
than complex
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10. Execution Characteristics
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Computer Architecture and Organization
• Operations performed
• Determine the functions to be performed by the processor and
its interaction with memory.
• Operands used
• The type of operand and the frequency of their use determine
the memory organizations for storing them and addressing
mode for accessing them.
• Execution sequencing
• These determines the control and pipeline organization.

11. Operations
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Computer Architecture and Organization
• A variety of study have been made to analyse the
behaviour of HLL programs.
• Assignment statement are predominate.
• Suggesting that simple movement of data is of high importance
• Conditional statements (IF, LOOP) are also high in number.
• Sequence control mechanism of instruction set is important.
• Such as compare and branch instructions.
• Procedure call-return is very time consuming.
• Some HLL instruction lead to many machine code
operations ( a compiled machine language program)

12. Weighted Relative Dynamic Frequency of HLL
Operations [PATT82a]
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Computer Architecture and Organization
Dynamic Occurrence
Machine-Instruction
Weighted
Memory-Reference
Weighted
Pascal C Pascal C Pascal C
ASSIGN 45% 38% 13% 13% 14% 15%
LOOP 5% 3% 42% 32% 33% 26%
CALL 15% 12% 31% 33% 44% 45%
IF 29% 43% 11% 21% 7% 13%
GOTO — 3% — — — —
OTHER 6% 1% 3% 1% 2% 1%

13. Operations
• The previous table suggests that procedure calls & returns
are the most time consuming operations in compiled HLL.
• Thus, it will be profitable to consider a way of implementing
those operations efferently
• Two parameters are significant
• The number of parameters & variables that a procedure deals with
• The depth of nesting
• The number of arguments are not large and high of
proportion of operation reference are local scalar variable.
• Program are confined to narrow windows of procedure-
invocation depth.
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14. Operands
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Computer Architecture and Organization
• Studies also looked at the dynamic frequency
occurrence of classes of a variable
• Mainly local scalar variables
• Optimisation should concentrate on accessing local
variables
Pascal C Average
Integer Constant 16% 23% 20%
Scalar Variable 58% 53% 55%
Array/Structure 26% 24% 25%

15. Implications
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Computer Architecture and Organization
• The attempt to make the instruction set architecture
closer to HLLs is not the most effective design strategy.
• Rather HLLs can be supported by optimising most used
and most time consuming features
• Generalizing from researches three elements emerge
that characterize RISC architecture
• Large number of registers or Compiler to optimize
• Intended to optimize operand referencing
• Studies shows there are several reference per HLL statements.
• Careful design of pipelines
• Because of high proportion of conditional branch & procedure
call instruction, a straightforward pipeline will be inefficient.
• Simplified (reduced) instruction set

16. Large Register File
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Computer Architecture and Organization
• Software solution
• Require compiler to allocate registers
• Allocate based on most used variables in a given time
• Requires sophisticated program analysis
• Hardware solution
• Have more registers
• Thus more variables will be in registers

17. The Hardware approach
• Most operand references are local scalars to procedure
• The problem is the definition of local changes with each
procedure call & return.
• Operations the occur frequently
• In every call, local variables must be saved from registers
into memory
• So that the registers can be used by the called programs.
• The solution is Register windows
• Use multiple small set of registers.
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18. Register windows
• The studies show that procedures
• Employs only a few passed parameters & local variable
• The depth fluctuates within relatively narrow range
• To exploit these properties, multiple small sets of
registers are used, each assigned to a different procedure.
• So that a procedure call automatically switches the
processor to use a different fixed-size windows of register
rather than saving registers into memory
• Windows for adjacent procedure overlaps to allow
parameter passing without the actual movement of data
• Windows itself is divided into fixed-size areas
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19. Register windows
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20. Global Variables
• Variables accessed by more than one procedure
• Two options
• Variables declared as global in HLL can be assigned
memory locations by the compiler
• For frequently accessed global variables this schema is inefficient
• To incorporate a set of global register in the processor
• Those registers would be fixed in number and available to all
procedures
• Compiler must decide which global variables should be assigned
to registers.
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21. Large Register File Vs Cache
Computer Architecture and Organization 21
Large Register File Cache
All local scalars Recently-used local scalars
Individual variables Blocks of memory
Compiler-assigned global variables Recently-used global variables
Save/Restore based on procedure nesting depth Save/Restore based on cache replacement algorithm
Register addressing Memory addressing

22. Compiler Based Register Optimization
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Computer Architecture and Organization
• Assume small number of registers (16-32)
• Optimizing use is up to the compiler
• HLL programs have no explicit references to registers
• usually - think about C - register int
• The objective of the compiler is to keep operands in
register and to minimize load & store operations.
• Assign symbolic or virtual register to each candidate
variable
• Map (unlimited) symbolic registers to real registers
• Symbolic registers that do not overlap can share real
registers
• If you run out of real registers some variables use
memory

23. Graph Coloring Approach
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Computer Architecture and Organization

24. Why CISC (1)?
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Computer Architecture and Organization
• Compiler simplification?
• Challenged by RISC researchers
• Complex machine instructions harder to exploit
• Optimization more difficult
• Smaller programs?
• Program takes up less memory but…
• Memory is now cheap
• May not occupy less bits, just look shorter in symbolic form
• More instructions on CISC require longer op-codes
• RISC favour register references which require fewer bits

25. Why CISC (2)?
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Computer Architecture and Organization
• Faster programs?
• A complex HLL operation may seem execute more quickly as a
single machine instruction rather than as a series of more
primitive instructions
• But it needs more complex control unit
• Microprogram control store larger
• Thus such single instructions take longer to execute
• It is far from clear that the trend to increasingly complex
instruction set is appropriate.

26. RISC Characteristics
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Computer Architecture and Organization
• One instruction per machine cycle
• machine cycle is the time it takes to fetch two operands from
registers, perform an ALU operation, and store the result in a
register
• Register to register operations
• Few, simple addressing modes
• Few, simple instruction formats
• Hardwired control unit.
• Fixed instruction format
• More compile time/effort

27. RISC v CISC
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Computer Architecture and Organization
• Not clear cut
• There is a growing realization that
• RISC design may benefit from the inclusion of some CISC
feature.
• CISC design may benefit from the inclusion of some RISC
feature.
• Many designs borrow from both philosophies
• No longer pure RISC or Pure CISC
• e.g. PowerPC and Pentium II

28. RISC Pipelining
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Computer Architecture and Organization
• Most instructions are register to register
• Two phases of execution
• I: Instruction fetch
• E: Execute
• ALU operation with register input and output
• For load and store
• I: Instruction fetch
• E: Execute
• Calculate memory address
• D: Memory
• Register to memory or memory to register operation

29. Effects of Pipelining
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Computer Architecture and Organization

30. Problems in comparison of RISC vs CISC
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Computer Architecture and Organization
• No pair of RISC and CISC that are directly comparable
level of technology, gate complexity, OS support.
• No definitive set of test programs. Performance varies
with program.
• Difficult to separate hardware effects from effects due to
skills in complier writing
• Most comparisons has been done on “toy” rather than
production machines
• Most commercial devices are a mixture

31. Department of Electrical and Computer Engineering
End of Chapter 7
Computer Architecture
and Organization