Winner of the best poster award at the 26th IEEE International Conference on High Performance Computing, Data, and Analytics 2019, held in Hyderabad, India. (Dec 17-20, 2019)

1. ACEP: An Accuracy-Configurable Carry Estimating Parallel Adder
Rajat Bhattacharjya, Vishesh Mishra, Saurabh Singh and Kaustav Goswami
Indian Institute of Information Technology Guwahati
INTRODUCTION RELATED WORKS MOTIVATION AND CONTRIBUTION
ALGORITHM METHODOLOGY APPLICATIONS
The motivation behind designing a new Approxi-
mate Binary Adder is as follows:
 Accuracy-Configuration: ACEP can be configured
differently for different accuracy requirements by
changing block sizes.
 Faster Computations: In ACEP, carry estimation
and sum generation is done in parallel in a non-
blocking manner which makes it much faster
than conventional adders.
 Applications end-results: We choose three popu-
lar end-applications that commonly benefit from
approximate methods. We see that ACEP produc-
es results that are better than other state-of-the-
art solutions by 12.3%. Also, we measure
speedup of end applications, which shows ACEP
to be 2.83x faster compared to baseline case.
Approximate adders can be broadly classified as
follows:
Non-Configurable Adders: The approximate binary
adders [5], [6], [7], [8] split the input operands into
two segments. In these types of adders, the LSBs
are approximately computed and MSBs are accu-
rately computed, thus producing results in lesser
time compared to the conventional ripple-carry ad-
der.
Accuracy-Configurable Adders: A few accuracy-
configurable adders have been proposed in the
past:
 RAP-CLA [9] splits the carry-lookahead circuit of a
CLA into two parts and switches them for approx-
imate or accurate mode.
 SARA [10] on the other hand uses its carry pre-
diction circuit to predict the carry of each block.
 BCSA [11] uses a carry predict unit to predict car-
ry and carry select unit to select whether to prop-
agate predicted carry or actual carry.
1.blockDivider (A[], B[], Cin, k):
2. Initialize: sum[k]
3. Cout = carryEstimator (A[k-1], B[k-1], A[k-2], B[k-2])
4. for i 0 to k in parallel do
5. sum[i] = A[i] ˆ B[i] ˆ Cin
6. Cin = (A[i] & B[i]) j ((A[i] ˆ B[i]) & Cin)
7. end for
8.return (sum, Cout)
REFERENCES
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ANALYSIS
Approximate computing in recent years has gar-
nered significant attention due to the massive data
deluge and requirements for fault-tolerant real-
time computations.
Towards this, there have been several techniques
proposed which have shown that often an approxi-
mate result with provable error bounds are desira-
ble rather than computing correct result from
scratch which can take significantly higher time.
APPROXIMATE ARITHMETIC CIRCUITS:
Approximation can be of various levels, such as:
 Full system approximation [1]
 Software level approximation [2]
 At level of code generation [3]
 At level of circuit systems like primary memory
and secondary storage devices [4].
Arithmetic circuits like adders and multipliers form
fundamental building blocks in all such approxi-
mate systems.
 Accuracy: We use standard error-metrics to com-
pare our design with other adders in addition to
Gaussian Smoothing and find that our results
show significant accuracy improvement of over
80.7% .
 Hardware Evaluation: ACEP shows significant
power and area savings compared to other ad-
ders in addition to improvement in delay. This is
mainly due to the carry-prediction logic em-
ployed in it.
Fig. III: Normalized Execution Time Obtained in SPEC CPU2006 Benchmarks
RESULTS
ACEP Probability Function :
The probability that the result generated through
ACEP has least error:
Carry estimator logic:
Cki = Aki-1 • Bki-1 + Aki-2 • Bki-2•Aki-1 + Aki-2 • Bki-2 • Bki-1
where; i Є[1:n=k].
CONCLUSION
In this paper, we present an accuracy-configurable adder (ACEP). Its major aspects can be listed as :
 It estimates carry-outs parallelly based on previous significant bits.
 It has significantly lower power consumption, delay and lesser area overhead compared to other state-
of-the-art approximate adders.
 When compared to the conventional ripple-carry adder, we find that our adder (ACEP) is 91.117% fast-
er than it when used in a best-case scenario.
In the near future, we wish to investigate our approximate addition technique for signed and floating
point operations.
Fig. II: Gaussian Smoothing
Fig. I: Kth
Block of ACEP
ACEP makes use of a divide and conquer approach
in addition to carry estimation. The following algo-
rithm describes the block division process:
(a) Original image, (b) Original image with noise, (c) RAP-CLA, PSNR=29.366dB & SSIM=0.7814 (d)
SARA, PSNR=26.79dB & SSIM=0.787 (e) BCSA, PSNR=33.9dB & SSIM=0.9142 (f) BCSA with ERU,
PSNR=37.837dB & SSIM=0.9482 (g) ACEP, PSNR=32.032dB & SSIM=0.9007
Fig. IV: Area Comparison Fig. V: Delay Comparison Fig. VI: Power Comparison
Fig. VI: Error Rate (%) Fig. VIII: Mean Error Distance (log) Fig. IX: Mean Relative Error Distance