Personal Information
Organization / Workplace
Bengaluru Area, India India
Occupation
FPGA& RTL DESIGN ENGINEER at MINDFLOW
Industry
Electronics / Computer Hardware
About
Overall experience of 2.8 years in RTL Design & FPGA board design
Experience in RTL design, Microarchitecture, On-chip debugging.
Experience in writing Verilog testbench for simulating RTL design before implementing on
FPGAs
Good working knowledge on Xilinx FPGA and development tools
•Good Experience SOC and ARM Architecture
•Excellent understanding of Protocols such as AMBA AXI4 .
• good knowledge of Modelsim, Questasim tools. Familiar with Object Oriented Programming.
Area of Interest:
Digital System Design,
VLSI Design,
Embedded System Design.
IP design & verification
SKILL SET
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HDL’s : Verilog
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EDA Tools : QuestaSim (Mentor...
- Presentations
- Documents
- Infographics
Verilog HDL
Mantra VLSI
•
11 years ago
Sequential Circuits - Flip Flops (Part 2)
Abhilash Nair
•
11 years ago
Verilog 語法教學
艾鍗科技
•
11 years ago
UAV Presentation
Ruyyan
•
15 years ago
SOC Verification using SystemVerilog
Ramdas Mozhikunnath
•
10 years ago
Spi master core verification
Maulik Suthar
•
11 years ago
IP Reuse Impact on Design Verification Management Across the Enterprise
DVClub
•
11 years ago
Uvm dcon2013
sean chen
•
11 years ago