Jaidev Kaushik

Bengaluru Area, India India

Post Silicon Validation Engineer at TESSOLVE, MTech (ECE/VLSI), BTECH (ECE), GATE

Electronics / Computer Hardware

I have completed MTECH in ECE with VLSI specialization. I have done my BTech (ECE) with gate qualified (gate score 459 in 2014).An international journal and an international conference proceeding have been published. 1+year Experienced in of TCAD, CADENCE and MATLAB tools. . Good knowledge of Verilog, Xilinx Spartan FPGA programming. Expertise in Digital Design and Advanced Verification Techniques Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools. Experienced with Xilinx EDK Platform. Knowledgeable in CMOS VLSI design, Verilog RTL coding, Memory designing. Knowledgeable in ASIC front end/back end design. Knowledgeable in Physical design flow. Experi...