1. LIST OF PUBLICATIONS
1. Microchip substance delivery devices having low-power electromechanical release mechanisms. U.S.
Patent 2016/0074323 A1, filed September 11, 2014, and issued March 17, 2016.
2. Thin, flexible microsystem with integrated energy source. U.S. Patent 2015/0287960 A1, filed July 2014,
2014, and issued October 8, 2015.
3. Dang B., Maria J., Chen Q., Nah J.-W., Andry P., Tsang C., Sakuma K., Tyberg C., Robertazzi R.,
Scheuermann M., Gaynes M., Knickerbocker J., “Assembly and Packaging of Non-Bumped 3D Chip Stacks
on Bumped Substrates”, 64
nd
Proc. Electronic Components and Technology Conf., 2014.
4. Dang B., Wright S.L., Maria J., Tsang C., Andry P.S., Wiggins L., Knickerbocker J., “NiFe-based Ball-
Limiting-Metallurgy (BLM) for Microbumps at 50 µm Pitch in 3D Chip Stacks”, 63
nd
Proc. Electronic
Components and Technology Conf., 2013.
5. Colgan E. G., Andry P., Dang B., Magerlein J.H., Maria J., Polastre R.P., Wakil J., “Measurement of
Microbump Thermal Resistance in 3D Chip Stacks”, 28
th
Semiconductor Thermal Measurement and
Management Symposium, 2012.
6. Knickerbocker J.K., Andry P.S., Colgan E., Dang B., Dickson T., Jahnes C., Liu Y., Maria J., Polastre R.P.,
Turlapi L., Tsang C., Webb B.C., Wiggins L., Wright S.L., “2.5D and 3D Technology Challenges and Test
Vehicle Demonstrations”, 62
nd
Proc. Electronic Components and Technology Conf., 2012.
7. Wright S.L., Tsang C., Maria J., Polastre R.P., Andry P., Knickerbocker J., “Micro-interconnection
reliability: thermal, electrical and mechanical stress”, 62
nd
Proc. Electronic Components and Technology
Conf., 2012.
8. Maria J., Dang B., Wright S.L., Tsang C.K., Andry P., Polastre R., Liu Y., Wiggins L., Knickerbocker J., “3D
Chip Stacking with 50 µm Pitch Lead-Free Micro-C4 Interconnections”, 61
st
Proc. Electronic Components
and Technology Conf., 2011.
9. Dang B., Andry P., Tsang C., Maria J., Farinelli M., Prabhakar A., Trzcinski R, Knickerbocker J., “CMOS
Compatible Thin Wafer Processing using Temporary Mechanical Wafer, Adhesive and Laser Release of
Thin Chips / Wafers for 3D Integration”, 60
th
Proc. Electronic Components and Technology Conf., 2010.
10. Sakuma S., Andry, P.S., Tsang, C.K., Wright, S.L., Dang B., Patel C.S., Webb B.C., Maria J., Sprogris E.J.,
Kang S.K., Polastre R.J., Horton R.R., Knickerbocker J.U., “3D Chip-Stacking Technology with Through-
Silicon Vias and Low-Volume Lead-Free Interconnects”, IBM J. Res. & Dev., 52 (6), 2008.
11. Sakuma K., Andry P.S., Dang B., Maria J., Tsang C.K., Patel C., Wright S.L., Webb B., Sprogris E., Kang
S.K., Polastre R., Horton R., Knickerbocker J.U., “3D Chip Stacking Technology with Low-Volume Lead-Free
Interconnections”, 57
th
Proceedings Electronic Components and Technology Conference, 2007.