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Algorithm and Architecture of Configurable Joint
Detection and Decoding for MIMO Wireless
Communications with Convolution Codes
Abstract:
This paper presents an algorithm and a VLSI architecture of a configurable joint detection and
decoding (CJDD) scheme for multi-input multi-output (MIMO) wireless communication systems
with convolutional codes. A novel tree-enumeration strategy is proposed such that the MIMO
detection and decoding of convolutional codes can be conducted in single stage using a tree-
searching engine. Moreover, this design can be configured to support different combinations of
quadrature amplitude modulation (QAM) schemes as well as encoder code rates, and thus can be
more practically deployed to real-world MIMO wireless systems. A formal outline of the
proposed algorithm will be given and simulation results for 16-QAM and 64-QAM with rate-1/2
and rate-1/3 codes will be presented showing that, compared with the conventional separate
scheme, the CJDD algorithm can greatly improve bit error rate (BER) performance with different
system settings. In addition, the VLSI architecture and implementation of the CJDD approach
will be illustrated. The architectures and circuits are designed to support configurability and
flexibility while maintaining high efficiency and low complexity. The post layout experimental
results for 16-QAM and 64-QAM with rate-1/2 and rate-1/3 codes show that, compared with the
previous configurable design, this architecture can achieve reduced or comparable complexity
with improved BER performance. The proposed architecture of this paper analysis the logic size,
area and power consumption using Xilinx 14.2.
Enhancement of the project:
Existing System:

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We will briefly review the system model of MIMO communications and tree-searching type
MIMO detection schemes. In addition, we will give an introductory overview for the
fundamental concept of joint MIMO detection and decoding of convolutional codes.
Fig. 1. Simplified system model of the MIMO communication system and the main concept of
JDD.
System Model and Tree-Searching Type MIMO Detection
Fig. 1 shows a simplified MIMO system with M transmit antennas. At the transmitter side,
source bits (information bits) are first sent to the channel encoder where, based on the encoder
structure, redundant bits are appended to generate coded bit streams. In the following, the bit
streams are mapped to the modulation points according to the specified modulation scheme, and
the M consecutive modulation points are arranged in an M × 1 transmit vector S and delivered
over the air.
Joint Detection and Decoding
Fig. 2(a) presents the concept of JDD for a MIMO system utilizing 16-QAM with rate-1/2
convolutional code and the corresponding trellis structure of the encoder. In this figure, [SX]
represents the state and two routes expanding from [SX] denote the input/output relation
assuming input bit 0 for the upper route and bit 1 for the lower one. As can be seen from this
example, originally, each tree node can possibly be extended to four child nodes assuming 16-

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QAM modulation after real-valued decomposition. However, due to the constraint of the trellis
structure, only two paths denoting the transition of [S0] → [S0] and [S0] → [S1] are valid and
are mapped to two out of four modulation points.
Fig. 2. Example of applying JDD to a system with (a) 16-QAM with rate-1/2 code and (b) 16-
QAM with rate-1/3 code.

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Disadvantages:
 BER performance is low
 efficiency of the design is low
 complex system
Proposed System:
Concepts of CJDD Approach:
The essential concept of the proposed CJDD algorithm lies in an innovative tree-enumeration
scheme such that the number of tree levels that must be considered together before moving
forward can be configured through system settings, including modulation scheme as well as
encoder code rate. Therefore, under various transmission conditions, different modulations
and/or coding rates could be chosen, and thus the operation for the CJDD can be adjusted
accordingly. Before formally outlining the proposed algorithm, in this section, we summarize the
system settings that might change the tree-searching behavior and explicitly define the control
parameters that are used to configure the operation of the algorithm.
Fig. 3. Example of the state transition for 16-QAM with rate-1/3 code.

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One example of state transition illustrating this analysis is presented in Fig. 3 assuming a system
with 16-QAM modulation (Mc = 4) and rate-1/3 code (n = 3). In this system, each node in the
tree structure contains two bits (Bl = 2) and each combination is mapped to one modulation
points. In addition, each trellis stage, i.e., a transition from one state to another state, generates
three bits by taking one source bit as the input.
CONFIGURABLE JOINT DETECTION AND DECODING ARCHITECTURE
Fig. 4. High-level overview of the proposed CJDD architecture.
Fig. 4 shows a high-level architectural overview of the proposed CJDD processor. As can be
seen from the figure, this design is comprised of three major processing elements, VSF, path
metric computer (PMC), and sorter. Furthermore, a number of registers are also used for storing
intermediate results. The architecture shown in Fig. 4 will be iterated multiple times to
enumerate the entire tree. To process any specific enumeration, at the beginning, states of the
survivor nodes will be fetched and sent to the VSF engine as the source states.
Advantages:
 improve the BER performance
 improve the design efficiency
 reduced system complexity

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Software implementation:
 Modelsim
 Xilinx ISE