Aneesh Raveendran

processor design microprocessor micro controller processor fpga vhdl branch prediction ip core mips computer architecture pipeline stalls pipe lining idealism uart transistors analog design electronic circuits universal asynchronous receive and transmit serial communication rs 232 instruction set control hazard data hazard tcl modelsim reversible logic gates fredkin gate feynman gate not gate toffolli gate reversible computing aligned memory access unaligned memory access memory access external fragmentation internal fragmentation pipe lining superscalar l1 cache arm fpu neon arm cortex-a8 rs232 ieee 802.15.1 protocol system on chip bluetooth on fpga soc bluetooth refcomm alu arithmetic and logic unit fetch module asic decoder execute cisc