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Memory aware task scheduling with communication overhead minimization for streamin applications on bus-based multiprocessor system-on chips
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Memory-Aware Task Scheduling with
Communication Overhead Minimization for
Streaming Applications on Bus-Based
Multiprocessor System-on-Chips
ABSTRACT:
Inter-core communication introduces overheads in task schedules on
Multiprocessor System-on-Chips (MPSoCs). Inter-core communication
overhead not only negatively impacts the timing performance but also
significantly degrades the memory usage for streaming applications
running on MPSoC architectures. By minimizing inter-core
communication overhead, a shorter period can be applied and system
performance (e.g., throughput, memory usage) can be improved. In this
paper, we focus on solving the problem of minimizing inter-core
communication overhead for streaming applications on bus-based
MPSoCs. The objective is to minimize inter-core communication overhead
while minimizing the overall memory usage. To solve the problem, we first
let tasks with intra-period data dependencies transform to inter-period
data dependencies so as to overlap the execution of computation and inter-
core communication tasks. By doing this, inter-core communication
overhead can be effectively removed. To minimize the overall memory
usage, we then perform schedulability analysis and obtain the bounds of
the times needed to reschedule each task. Based on the schedulability
analysis, we formulate the scheduling problem as an integer linear
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programming (ILP) model and obtain an optimal schedule. In addition, we
propose a heuristic approach to efficiently obtain a near-optimal solution.
We conduct experiments on a set of benchmarks from both real-life
streaming applications and synthetic task graphs. The experimental results
show that the proposed approach can significantly reduce the schedule
length and improve the memory usage compared with the previous work.
EXISTING SYSTEM:
We focus on solving the problem of minimizing inter-core communication
overhead for streaming applications on bus-based MPSoCs. The objective
is to minimize inter-core communication overhead while minimizing the
overall memory usage. To solve the problem, we first let tasks with intra-
period data dependencies transform to inter-period data dependencies so
as to overlap the execution of computation and inter-core communication
tasks. By doing this, inter-core communication overhead can be effectively
removed. To minimize the overall memory usage, we then perform
schedulability analysis and obtain the bounds of the times needed to
reschedule each task. Based on the schedulability analysis, we formulate
the scheduling problem as an integer linear programming (ILP) model and
obtain an optimal schedule The communication overhead poses a challenge
for bus-based multi-core hard real-time systems, since most of the existing
theoretically optimal scheduling techniques on multi-core architectures
assume zero cost for inter-core communications.
PROPOSED SYSTEM:
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The proposed approach can significantly reduce the schedule length and
improve the memory usage compared with the previous work.
For memory-aware task scheduling, several techniques have been proposed
to optimize the performance of memory system, and to reduce the memory
access of real-time applications. We also proposed a heuristic algorithm to
efficiently obtain a near optimal solution. Experimental results show that
the proposed approach can significantly reduce the schedule length and
improve the memory usage compared with representative techniques.
CONCLUSION:
We have considered the task scheduling problem of removing inter-core
communication overhead for streaming applications running on MPSoC
architectures. We totally removed inter-core communication overhead by
rescheduling tasks with intra-period data dependencies into inter-period
data dependencies, such that the execution of computation and that of
inter-core communication tasks can be overlapped and a shorter period
can be applied. We performed analysis and presented an ILP model to
obtain an optimal schedule with the minimum memory usage. We also
proposed a heuristic algorithm to efficiently obtain a near optimal solution.
Experimental results show that the proposed approach can significantly
reduce the schedule length and improve the memory usage compared with
representative techniques.