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DDR4 NVDIMM Standardization:
DDR4 NVDIMM Standardization:
DDR4 NVDIMM Standardization:
DDR4 NVDIMM Standardization:
Now and Future
Now and Future
Server Forum 2014 Copyright © 2014 Micron Technology, Inc
https://www.jedec.org/sites/default/files/files/Brett_Williams_Server_Forum_2014.pdf
NVDIMM Definition
NVDIMM Definition
• One of several Hybrid DIMM versions
• RDIMM/LRDIMM-like DRAM module with storage
memory components, controller and bus isolation
• Plugs into a standard DIMM socket
• No direct access to on-module storage memory (NAND)
– Only used for DRAM backup/restore (limited by protocol &
controller)
• On-module storage memory provides persistence in
event of power fail
• Backup power source required
– Tethered ultracap or back-up power through 12V pins
Non
Non-
-Volatile DIMM (NVDIMM)
Volatile DIMM (NVDIMM)
Persistent Memory Enabled by DRAM + NAND
Persistent Memory Enabled by DRAM + NAND
• HW Architecture
– RDIMM with bus isolation,
storage memory, and
controller
• FW Architecture
– Save on Power loss
– Restore on Reboot
– “SAVE” operation through
I2C command or “SAVE”
HW signal
UltraCap Module
Self-contained energy source
for operation during power
failure
Onboard DRAM &
NAND
DRAM performance
Oil & Gas
Exploration
Medical
Research
Financial
Transactions
Power Loss
Events
Big Data
Analytics
Financial Data
Integrity
HW signal
• Power-fail backup source
– Typically 1:1 requirement
to NVDIMM
– Tethered ultracap pack
– 12V DIMM connector
DRAM performance
with data persistence
Integrated
Controller
NAND management
and high speed DMA
Mux
Bus Isolation for
backup and restore
12V
Energy source,
DIMM connector
The Case for NVDIMM
The Case for NVDIMM
Picoseconds Nanoseconds Microseconds Milliseconds Seconds
CPU
Cache
SATA
SSD
SAS
SSD
HDD
Significant hierarchy gap exists in current
scale-out architectures
DRAM
PCIe
SSD
Performance
Persistence
Endurance
• Speed/performance driving large data sets to be stored in “warm” or “hot” locations
(NVDIMM, PCI SSDs, etc.)
• NVDIMM used as storage cache acceleration in many instances
• Enterprise applications using real-time processing to capture, analyze, and respond
intelligently to changing events
• Reliability/uptime is critical for enterprise IT resources
• Gaining momentum in several application spaces
Maintaining QoS while supporting increasingly demanding enterprise workloads are
driving need for higher memory performance and density.
DDR4 12V Power Pins (1, 145)
DDR4 12V Power Pins (1, 145)
Standardized
Standardized
• Provides NVDIMM power for two possible situations
• Tethered ultracap charging
• Central back-up power using 12V pins during power loss
• Energy provided only for NVDIMM “SAVE” operation
• Ultracap charging
• Charging will be significantly faster than 1.2V source
• Charging will be significantly faster than 1.2V source
• Central back-up power
• Eliminates need for individual ultracaps
• Allows for higher number NVDIMM/system
• Allows for higher density NVDIMMs
• System required to handle status monitoring and health of
backup power
• Mechanism to get this information to NVDIMM
controller
DDR4 12V Power Pin Details
DDR4 12V Power Pin Details
Possible Future Consideration
Possible Future Consideration
• Central back-up power scenario
• More definition/standardization required
• Minimum voltage specification
• Amount of energy available
• Amount of energy available
• Length of up time after system power loss
• Back-up power health and status monitoring details
• System needs details to determine:
• Capability of backup source
• Number and size of NVDIMMs the system can
support
DDR4
DDR4 SAVE_n
SAVE_n Pin (230)
Pin (230)
Standardized
Standardized
• Similar to DDR3 HW signal used today to initiate
NVDIMM backup
• Similar DDR3 system requirements prior to
activating “SAVE_n” signal
• DRAM must be placed in self-refresh
• NVDIMM must be ready to perform a backup
• Sufficient space in storage memory
• Sufficient backup power
• Use of “SAVE_n” is the quickest way to initiate a
backup
Operation Complete HW Signal
Operation Complete HW Signal
Possible Future Consideration
Possible Future Consideration
• Current notice of completed backup or restore
• Polling NVDIMM status registers
• Polling status reduces operational performance
• Standardizing an operation complete HW signal
• Could be used for multiple operations
• Initialization
• Initialization
• Save
• Restore
• Possible alternatives
• Bidirectional signal (SAVE_n)
• Separate pin multiplexed with other events such as (ALERT_n or
Event)
• Higher system performance than polling
• Only interrupt CPU when operation complete
• Less time spend in servicing operation
NVDIMM FW
NVDIMM FW
Possible Future Consideration
Possible Future Consideration
• NVDIMM FW Control
• Initialization
• Backup
• Restore
• Status
• Errors
Application
3rd Party SW
Proprietary SW
SW Stack
BIOS/UEFI
OS
• Errors
• Ultracap Management
• Storage Memory
Management
• Standardized FW features
• Not necessarily a
standard FW interface
• Simplifies MRC, BIOS,
and OS/Driver support
MRC
Driver
NVDIMM FW
Recognition
Configuration
Initialization
Operational Control
Features
Memory table
Application
Interface
HW Control
Status
Summary
Summary
• NVDIMM fulfills a need in the storage hierarchy
• Standardization opens up new growth opportunities
• Current 12V standard allows for efficient ultracap charging
and a central backup power source
and a central backup power source
• SAVE_n standard sets a efficient interface to signal a backup
• More standardization is possible in several areas
• Standardization drives wider adoption
• As more applications discover the benefits of NVDIMM new
areas of standardization will probably follow

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2014 DDR4 NVDIMM Standardization Now and Future.pdf

  • 1. DDR4 NVDIMM Standardization: DDR4 NVDIMM Standardization: DDR4 NVDIMM Standardization: DDR4 NVDIMM Standardization: Now and Future Now and Future Server Forum 2014 Copyright © 2014 Micron Technology, Inc https://www.jedec.org/sites/default/files/files/Brett_Williams_Server_Forum_2014.pdf
  • 2. NVDIMM Definition NVDIMM Definition • One of several Hybrid DIMM versions • RDIMM/LRDIMM-like DRAM module with storage memory components, controller and bus isolation • Plugs into a standard DIMM socket • No direct access to on-module storage memory (NAND) – Only used for DRAM backup/restore (limited by protocol & controller) • On-module storage memory provides persistence in event of power fail • Backup power source required – Tethered ultracap or back-up power through 12V pins
  • 3. Non Non- -Volatile DIMM (NVDIMM) Volatile DIMM (NVDIMM) Persistent Memory Enabled by DRAM + NAND Persistent Memory Enabled by DRAM + NAND • HW Architecture – RDIMM with bus isolation, storage memory, and controller • FW Architecture – Save on Power loss – Restore on Reboot – “SAVE” operation through I2C command or “SAVE” HW signal UltraCap Module Self-contained energy source for operation during power failure Onboard DRAM & NAND DRAM performance Oil & Gas Exploration Medical Research Financial Transactions Power Loss Events Big Data Analytics Financial Data Integrity HW signal • Power-fail backup source – Typically 1:1 requirement to NVDIMM – Tethered ultracap pack – 12V DIMM connector DRAM performance with data persistence Integrated Controller NAND management and high speed DMA Mux Bus Isolation for backup and restore 12V Energy source, DIMM connector
  • 4. The Case for NVDIMM The Case for NVDIMM Picoseconds Nanoseconds Microseconds Milliseconds Seconds CPU Cache SATA SSD SAS SSD HDD Significant hierarchy gap exists in current scale-out architectures DRAM PCIe SSD Performance Persistence Endurance • Speed/performance driving large data sets to be stored in “warm” or “hot” locations (NVDIMM, PCI SSDs, etc.) • NVDIMM used as storage cache acceleration in many instances • Enterprise applications using real-time processing to capture, analyze, and respond intelligently to changing events • Reliability/uptime is critical for enterprise IT resources • Gaining momentum in several application spaces Maintaining QoS while supporting increasingly demanding enterprise workloads are driving need for higher memory performance and density.
  • 5. DDR4 12V Power Pins (1, 145) DDR4 12V Power Pins (1, 145) Standardized Standardized • Provides NVDIMM power for two possible situations • Tethered ultracap charging • Central back-up power using 12V pins during power loss • Energy provided only for NVDIMM “SAVE” operation • Ultracap charging • Charging will be significantly faster than 1.2V source • Charging will be significantly faster than 1.2V source • Central back-up power • Eliminates need for individual ultracaps • Allows for higher number NVDIMM/system • Allows for higher density NVDIMMs • System required to handle status monitoring and health of backup power • Mechanism to get this information to NVDIMM controller
  • 6. DDR4 12V Power Pin Details DDR4 12V Power Pin Details Possible Future Consideration Possible Future Consideration • Central back-up power scenario • More definition/standardization required • Minimum voltage specification • Amount of energy available • Amount of energy available • Length of up time after system power loss • Back-up power health and status monitoring details • System needs details to determine: • Capability of backup source • Number and size of NVDIMMs the system can support
  • 7. DDR4 DDR4 SAVE_n SAVE_n Pin (230) Pin (230) Standardized Standardized • Similar to DDR3 HW signal used today to initiate NVDIMM backup • Similar DDR3 system requirements prior to activating “SAVE_n” signal • DRAM must be placed in self-refresh • NVDIMM must be ready to perform a backup • Sufficient space in storage memory • Sufficient backup power • Use of “SAVE_n” is the quickest way to initiate a backup
  • 8. Operation Complete HW Signal Operation Complete HW Signal Possible Future Consideration Possible Future Consideration • Current notice of completed backup or restore • Polling NVDIMM status registers • Polling status reduces operational performance • Standardizing an operation complete HW signal • Could be used for multiple operations • Initialization • Initialization • Save • Restore • Possible alternatives • Bidirectional signal (SAVE_n) • Separate pin multiplexed with other events such as (ALERT_n or Event) • Higher system performance than polling • Only interrupt CPU when operation complete • Less time spend in servicing operation
  • 9. NVDIMM FW NVDIMM FW Possible Future Consideration Possible Future Consideration • NVDIMM FW Control • Initialization • Backup • Restore • Status • Errors Application 3rd Party SW Proprietary SW SW Stack BIOS/UEFI OS • Errors • Ultracap Management • Storage Memory Management • Standardized FW features • Not necessarily a standard FW interface • Simplifies MRC, BIOS, and OS/Driver support MRC Driver NVDIMM FW Recognition Configuration Initialization Operational Control Features Memory table Application Interface HW Control Status
  • 10. Summary Summary • NVDIMM fulfills a need in the storage hierarchy • Standardization opens up new growth opportunities • Current 12V standard allows for efficient ultracap charging and a central backup power source and a central backup power source • SAVE_n standard sets a efficient interface to signal a backup • More standardization is possible in several areas • Standardization drives wider adoption • As more applications discover the benefits of NVDIMM new areas of standardization will probably follow