Testing of Logic Circuits document discusses: 1) The need to test logic circuits when first developed and when manufactured to check for flaws. 2) Common testing techniques like combinational/sequential circuit testing, fault models, path sensitizing, scan path testing, and boundary scan testing. 3) Fault models assume faults make wires permanently stuck at logic 0 or 1. 4) Path sensitizing activates paths so signal changes directly impact outputs to test for faults.

1. Testing of Logic Circuits
Mr. S. M. Karve
Department of Electronics & Telecommunication
Engineering

2. 
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NEED OF TESTING CIRCUIT
There are several reasons for testing a logic circuit.
When the circuit is first developed, it is necessary to verify that
the designed circuit meets the required functional and timing
specifications.
When multiple copies are manufactured, it is essential to test
each copy to ensure that the manufacturing process has not
introduced any flaws.
The basis of all testing techniques is to apply predefined sets of
inputs, called tests, to a circuit and compare the outputs observed
with the patterns that a correctly functioning circuit is supposed to
produce.
The challenge is to derive a relatively small number of tests that
provide an adequate indication that the circuit is correct.

3. 
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TESTING TECHNIQUES
Types of Testing Circuits
Combinational Circuit Testing
 Fault Model
 Path Sensitizing
 Random Test
Sequential Circuit Testing
 Scan Path Test
 Built-in Self Test (BIST)
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 Built-in Logic Block Observer (BIBLO)
Signature Analyzer
 Boundary Scan Test (BST)

4. 
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FAULT MODEL
A circuit functions incorrectly when there is something wrong with
it, such as a transistor fault or an interconnection wiring fault.
A transistor switch can break so that it is permanently either
closed or open.
A wire in the circuit can be shorted to VDD or to ground, or it can
be simply broken.
There can be an unwanted connection between two wires.
Fortunately, it is possible to restrict the testing process to some
simple faults, and obtain generally satisfactory results.

5. 
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STUCK AT MODEL
A good model for representing faults is to assume that all faults
manifest themselves as some wires (inputs or outputs of gates)
being permanently stuck at logic value 0 or 1.
Consider a wire, w.
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If w has an undesirable signal that always corresponds to the logic value
0, by saying that w is stuck-at-O, which is denoted as w/0.
If w has an undesirable signal that is always equal to logic 1, then w is
stuck-at-1, which is denoted as w/1.
 A circuit can have either a single fault or possibly many faults.
Dealing with multiple faults is difficult because each fault can
occur in many different ways. A pragmatic (practical) approach is
to consider single faults only.

6. STUCK AT MODEL

7. 
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PATH SENSITIZING
Previous approach is not feasible from the practical point of view,
because if there are too many wires then it will have too many
faults.
A better alternative is to deal with several wires that form a path
as an entity that can be tested for several faults using a single
test.
It is possible to activate a path so that the changes in the signal
that propagates along the path have a direct impact on the output
signal.

8. PATH SENSITIZING
 The path is activated by ensuring that other paths in the circuit do
not determine the value of the output f.
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If w2 =1 then b depends only on the value a.
If w3 = 0 so that it does not affect the NOR gate,
If w4 =1 it not affect the AND gate.
Then if w1 = 0 the output will be f = 1,
whereas w1 = 1 will cause f = 0.
Instead of saying that the path from w1 to f is activated, a more
specific term is used, which says that the path is sensitized.

9. PATH SENSITIZING
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To sensitize a path through an input of an AND or NAND gate, all
other inputs must be set to 1.
To sensitize a path through an input of an OR or NOR gate, all
other inputs must be 0.

10. SCAN PATH TESTING

11. SCAN PATH TESTING
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Scan path, uses multiplexers on flip-flop
inputs to allow the flip-flops to be used
either independently during normal
operation of the sequential circuit, or as a
part of a shift register for testing purposes.
Figure presents the general scan-path
structure for a circuit with three flip-flops. A
2-to-l multiplexer connects the D input of
each flip-flop either to the corresponding
next-state variable or to the serial path that
connects all flip-flops into a shift register.
The control signal Normal/Scan selects the
active input of the multiplexer.
During the normal operation the flip-flop
inputs are driven by the next-state
variables, Y1 , Y2, and Y3 •.

12. SCAN PATH TESTING
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For testing purposes the shift-register
connection is used to scan in the portion
of each test vector that involves the
present-state variables, Y1, Y2, and Y3.
This connection has Qi connected to
Di+1 .
The input to the first flip-flop is the
externally accessible pin Scan-in.
The output comes from the last flip-flop,
which is provided on the Scan-out pin.
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13. 
SCAN PATH TESTING
Example
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14. BUILT-IN SELF TEST
The circuit with self-testable facility, is called as built-in self-test
(BIST).
 Figure shows a possible BIST arrangement in which a test vector
generator produces the test vectors that must be applied to the
circuit under test (CUT).
15

15. n
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BUILT-IN SELF TEST
LFSR (Linear Feedback Shift Register)
The circuit in Figure is linear feedback shift registers (LFSRs).
Using feedback from the various stages of an n-bit shift register,
connected to the first stage by means of XOR gates, it is possible to
generate a sequence of 2 -1 patterns that have the characteristics of
randomly generated numbers.

16. 
BUILT-IN SELF TEST
SIC (Single Input Compressor Circuit )
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17. 
BUILT-IN SELF TEST
MIC (Multiple Input Compressor Circuit)
Above figure illustrates how four inputs, P0 through P3, can be added to
the basic circuit of previous figure.
Again the four-bit signature provides a good mechanism for
distinguishing among different sequences of four-bit patterns that may
appear on the inputs of this multiple-input compressor circuit (MIC).

18. BUILT-IN SELF TEST
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MIC
(Multiple Input
Compressor
Circuit)
SIC
(Single Input
Compressor
Circuit)
PRBSG
(Pseudorandom
Binary
Sequence
Generator)

19. BUILT-IN SELF TEST
Example :
BIBLO: Built-In Logic Block Observer
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20. BUILT-IN SELF TEST
Example :
Signature Analysis
 Signature Analysis using BIBLO
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21. BOUNDARY SCAN TEST
 The testing techniques discussed in the previous
sections are equally applicable to circuits that are
implemented on single chips.
 A circuit can be tested only if it is possible to apply the
tests to it and observe the outputs produced.
 When chips are soldered onto a printed circuit board, it
often becomes impossible to attach test probes to pins.
 This obstructs the testing process unless some indirect
access to the pins is provided. The scan-path concept
can be extended to the board level to deal with the
problem. 22

22. BOUNDARY SCAN TEST
 Suppose that each primary input or output pin on a chip
is connected through a D flip-flop and that a provision is
made for a test mode in which all flip-flops can be
connected into a shift register.
 Then the test information can be scanned in and
scanned out using the shift-register path, via two pins
that serve as serial input and output.
 Connecting the serial output pin of one chip to the serial
input pin of another chip results in the pins of all chips
being connected into a board-wide shift register for
testing purposes. 23

23. --definition of simulation process
tb : process
begin
num1<="0010"; --num1 =2
num2<="1001"; --num2 =9
wait for 2 ns;
num1<="1001"; --num1 =9
num2<="0010"; --num2 =2
wait for 2 ns;
num1<="1010"; --num1 =10
num2<="1010"; --num2 =10
--more input combinations can be given here.
wait;
end process tb;
end;
Test Bench for Adder

24. LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_decoder IS
END tb_decoder;
ARCHITECTURE behavior OF tb_decoder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder
PORT(
a : IN std_logic_vector(1 downto 0);
b : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal b : std_logic_vector(3 downto 0);
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: decoder PORT MAP (
a => a,
b => b
);
Test Bench for Comparator
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= "00";
wait for 100 ns;
a <= "01";
wait for 100 ns;
a <= "10";
wait for 100 ns;
a <= "11";
wait;
end process;
END;

25. LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_mux IS
END tb_mux;
ARCHITECTURE behavior OF tb_mux IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux_4to1
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';
--Outputs
signal Z : std_logic;
Test Bench for Multiplexer
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= '1';
B <= '0';
C <= '1';
D <= '0';
S0 <= '0'; S1 <= '0';
wait for 100 ns;
S0 <= '1'; S1 <= '0';
wait for 100 ns;
S0 <= '0'; S1 <= '1';
wait for 100 ns;
S0 <= '0'; S1 <= '1';
wait for 100 ns;
end process;
END;

26. VLSI DESIGN FLOW WITH REFERENCE TO XILINX TOOL
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27. THANK YOU
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