This document discusses data types in VHDL. It begins by explaining that data types can be classified into scalar, composite, and user-defined types. Scalar types refer to types that have a single value and include discrete types like integers, floating point, and physical types. Composite types have a regular structure like arrays and records. The document then provides more details about scalar types like integers, booleans, characters and examples of how to declare and use different data types in VHDL code.

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– Second level
• Third level
– Fourthg i t a l D e s i g n u s i n g V H D L
D i level
Session Five
» Fifth level
Introduced by
Cairo-Egypt
Session Five Version 03 – June 2012 1

2. about Start Group
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Mahmoud Abdellatif
– Second level
Alaa Salah Shehata
Mohamed level
• Third Salah
Mohamed Talaat
– Fourth level
» Fifth level
start.courses@gmail.com www.slideshare.net/StartGroup
www.facebook.com/groups/start.group
www.startgroup.weebly.com Start.courses@gmail.com
+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011
+ 02 0128-0090250 A.S
Session Five 2

3. Outline
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– Second level
• Third level
Data Types
- Scalar
- Composite
- User defined
Modeling Memories
5
– Fourth level
Mini Project no.2 Scrambler
» Fifth level
Session Five 3

4. Outline
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Data Types
- Scalar
– Second level - Composite
- User defined
• Third level Modeling Memories
– Fourth level
Mini Project no.2 Scrambler
» Fifth level
Session Five 4

5. Data Types Hierarchy
Natural
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Integers
Positive
– Second level Discrete
Boolean
• Third level
Enumeration Character
– Fourth level
Scalar
» Fifth level Physical Time Bit
Data Types
Floating Point Real
Bit Vector
Array
Composite String
Record
File
Session Five 5

6. Data Types
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-Type declaration is made inside architecture declaration, entity declaration, process declaration
– Second level
-VHDL is a strongly typed language, meaning that data objects of different types cannot be
assigned to one another without the use of a type conversion function.
• Third level
Data Types can be classified into:
– Fourth level
1–Scalar types » Fifth level
Refers to all types whose objects have a single value at any time instant.
2–Composite types
Refers to types that have a regular structure consisting of elements of the same type
such as array or elements of different types such as record.
3–User defined types
Types that are defined by default and to be defined by the user before using.
Session Five 6

7. Outline
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Data Types
- Scalar
– Second level - Composite
- User defined
• Third level Modeling Memories
– Fourth level
Mini Project no.2 Scrambler
» Fifth level
Session Five 7

8. Data Types [Scalar Types]
-Refers to all types whose objects have a single value at any time instant.
1- Discrete types
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-Enumerated types
a–Bit
– Second level defines two standard logic values (‘0’, ‘1’)
b–Boolean
• Third defined as FALSE or TRUE
level
c–Character
– Fourth level
type enumerates the ASCII character set
characterlevel …. ‘A’ , ‘B’, ...) ;
» Fifth ( ‘@’,’#’,
-Integer
Range -2147483648 to 2147483648
2–Floating Point
-Real
has no meaning in synthesis so it is only used for simulation.
Range -1.0E308 to 1.0E308
3–Physical types
Physical types represent measurements of some quantity such as time, length,
resistance…
Session Five 8

9. Data Types [Scalar] >>Boolean
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Boolean Type
– Second level
Type Boolean is used in the conditional operations
Boolean ( false , true ) ;
• Third level
Logical functions such as equality (=) and comparison (<) functions return a BOOLEAN value.
– Fourth level
Logical operators returns BOOLEAN if operands are also Boolean type.
Example » Fifth level
Evaluate the following relational expression:
”1011” < ”110”. Comment
The expression evaluates to true.
Session Five 9

10. Example 21
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– Second level
entity ex_enum is
Port ( • Third level
inp1 : in STD_LOGIC;
– Fourth
inp2 : in STD_LOGIC; level
outp1 : out Boolean;
outp2 : out Character; level
» Fifth
outp3 : out string(1 to 5) );
end ex_enum;
architecture Behavioral of ex_enum is
Begin
outp1 <= „true‟ when inp1 < inp2 else „false‟ ;
outp2 <= „t‟ when inp1 < inp2 else „f‟ ;
outp3 <= “equal” when inp1=inp2 else “notEQ”;
end Behavioral;
Session Five 10

11. Example 22
Real
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– Second level
• Third level
entity ex_enum is
Port ( – Fourth level
inp1 : in STD_LOGIC;
» Fifth level
inp2 : in STD_LOGIC;
outp : out real );
end ex_enum;
architecture Behavioral of ex_enum is
Begin
outp<= 1.5 when inp1 < inp2 else 2.5;
end Behavioral;
Session Five 11

12. Data Types [Scalar] >>Integers
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Integers
– Second level
integer range -2147483648 to 2147483648 ;
-231 to 231
• Third level
Example
– Fourth level
Signal counter : integer range 0 to 15 ;
» Fifth level
Note
The implementation of the type integer in the synthesis and depends on the range specified by the
user.
Subtypes natural and positive are predefined subtypes of integer.
Subtype natural is integer range 0 to integer‟high;
Subtype positive is integer range 1 to integer‟high;
Session Five 12

13. Data Types [Scalar] >>Physical
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Predefined Physical Type
– Second level
What about time, How it is represented inside VHDL
Note • Third level
physical types are not synthesizable
– Fourth level
» Fifth level
type time is range -2147483647 to 2147483647
Units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
Session Five 13

14. Example 23
Which Lines true ?
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– Second level
PROCESS (X)
• Third level
variable a:integer;
variable b: integer range 0 to 15;
type int is
– Fourth level
range -10 to 10;
variable d: int; » Fifth level
BEGIN
a := 1;
b := -1;
d := -12;
a := 1.0;
a := -1;
b := 10;
d := a;
END PROCESS;
Session Five 14

15. Outline
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Data Types
- Scalar
– Second level - Composite
- User defined
• Third level Modeling Memories
– Fourth level
Mini Project no.2 Scrambler
» Fifth level
Session Five 15

16. Data Types [Composite Types]
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-Refers to all types whose objects have a single value at any time instant.
– Second level
1- Array types
Multiple elements of the same type
• Third level
a–Bit Vector
– Fourth level 1D array type each element being of type bit
predefined as
Its size defined at declaration
» Fifth level bit_vector(4 downto 0);
signal x :
b–String
if we need to write string of characters
signal st : string(1 to 5);
2– Record types
Multiple elements of the different types
Session Five 16

17. Data Types [Composite] >>Array
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Group elements of same type.
Syntax
– Second level
Type <type_name> is array <range> of <data_type>; 7 21 0
• Array
Example 1D Third level 0
– Fourth level . 1
type data is array (7 downto 0) of bit ;
signal D_bus : data Fifth level
» ; .
D_bus <= “10101010”;
.
2D Array 15
Architecture
type memory is array (0 to 15) of std_logic_vector(7 downto 0);
signal word : memory ;
….
Begin
word (5) <= “10010110” ;
word (15,4) <= „1‟ ;
Session Five 17

18. Data Types [Composite] >>Record
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Group elements of possibly different types
Elements are indexed via field names
– Second level
Syntax
• Third level
type <type_name> is record
– Fourth level
identifier: type; signal tx_packet : packet;
identifier: type; tx_packet.ID <= 3 ;
…
» Fifth level tx_packet.PAYLOAD <= “1000..10101”;
end record;
Example Data Packet
type packet is record
ID : integer range 0 to 15 ;
C : std_logic ;
SOF : std_logic_vector(7 downto 0) ;
PAYLOAD : std_logic_vector( 127 downto 0) ;
CRC : std_logic_vector(3 downto 0) ;
EOF : std_logic_vector(7 downto 0);
end record ;
Session Five 18

19. Data Types Assigning values
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Here is summary of valid assigning values
– Second level
type word is array (0 to 31) of std_logic;
• Third level
type byte is array (7 downto 0) of std_logic;
type memory is array (0 to 15) of std_logic_vector(7 downto 0);
– Fourth
Signal y : std_logic;level
Signal xv : std_logic _vector(7 downto 0);
» Fifth level
Signal D_bus : word;
Signal mem1 : memory;
Signal x : byte;
------
Y <= xv(4);
Y <= „1‟;
mem1(5) <= "10010110" ;
mem1(15,4) <= '1' ;
y := x(5);
Session Five 19

20. Outline
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Data Types
- Scalar
– Second level - Composite
- User defined
• Third level Modeling Memories
– Fourth level
Mini Project no.2 Scrambler
» Fifth level
Session Five 20

21. Data Types [User defined Types]
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Types that are defined by default and to be defined by the user before using, such as encoding
FSM next and present states.
– Second level
Syntax
• Third level
Type <type_name> is (value1, value2, )
– Fourth level
» Fifth level
Most often used in the encoding of FSM states.
When encoding the states of the FSM of the control
unit in a microprocessor, one can define it as follows.
Type states is (reset, fetch, decode, excute, store)
Signal P_state : states;
Session Five 21

22. Data Conversion
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VHDL is a strongly
edit Master that data objects of
– Second level
to one another without the use of a type conversion function.
• both integer variables, the assignment
If A and B are Third level
a := b – ‘1’ ;
+ Fourth level illegal because ‘1’ is of type bit.
is
» Fifth level
Example
SIGNAL a,b : IN integer;
SIGNAL y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);
-- to change from integer to std_logic function conv_integer + range
a <=conv_integer(y); --to change from std_logic to integer
Session Five 22

23. Outline
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Data Types
- Scalar
– Second level - Composite
- User defined
• Third level Modeling Memories
– Fourth level
Mini Project no.2 Scrambler
» Fifth level
Session Five 23

24. Modeling Memories
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– Second level
First we will think how to make a RAM unit, You may think that we need :
• Clock Source for Synchronization
•
• Third level
Enable to control writing on memory
• – Fourth level
Enable to control reading from memory
• Address to control which data to read or write
• Input data » Fifth level
• Output data
Session Five 24

25. Lab 06
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Title:
RAM with separate read and write ports
Goal:
– Second level

• Dealing with Memories
Third levelproject on Xilinx ISE
 Creating new
 – Fourth level
Synthesis Reports on Xilinx ISE
 Simulation of Memories
» Fifth level
Tutorial [2]
Slides
Session Five 25

26. Lab 06
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RAM with separate read and write ports
– Second level
• Third
Assignment level
– Fourth level
» Fifth level
Session Five 26

27. Lab 06
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RAM with internal address control
– Second level
• Third
Assignment level
– Fourth level
» Fifth level
Session Five 27

28. Lab 06
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Synchronous 16 * 8 ROM
– Second level
• Third
Assignment level
– Fourth level
» Fifth level
Session Five 28

29. Start Notes [Synthesis Notes]
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Integers Precautions
• IF not be Unconstrained
– Second level
Synthesizing data types
wide resources for them
• Use in Constants.
• Third level • Don’t use in interfaces
Integers used in care
– Fourth
usually in constants. Also level
we use std_logic » Fifth level
and
std_logic_vector instead of User defined data types
bit and bit_vector and also Translated into certain no. of bits
we will use signed and
unsigned only for internal Type sum is (may, june, july, august);
calculations , Signals of -- May = “00”
User types translated into -- June = “01”
certain no. of bits. -- July = “10”
-- August = “11”
Session Five 29

30. Outline
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Data Types
- Scalar
– Second level - Composite
- User defined
• Third level Modeling Memories
– Fourth level
Mini Project no.2 Scrambler
» Fifth level
Session Five 30

31. Mini Project
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1) One purpose of scrambling is to reduce the length of strings of 0s or 1s in a
transmitted signal, since a long string of 0s or 1s may cause transmission
– Second level
synchronization problems, i.e. cause the clock regeneration at the receiver more
difficult.
• Third level
2) Also for making the transmitted signal more secured.
– Fourth level
» Fifth level
B(i)=[A(i)+C(i)]mod2
A(i) : Input to the scrambler.
A(i) B(i)
Scrambler
B(i) : Scrambled code word the
Output of the scrambler
C(i) : Output of the Pseudo-random sequence generation
Session Five 31

32. Mini Project
Pseudo-random sequence generation
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C(i) will be Xored with the input of the scrambler A(i) generating the scrambled
– Second level
output B(i)
• Third level
In Communication expression XORing is defined as module-2
– Fourth level
B(i)=[A(i)+C(i)]mod2
» Fifth level
Session Five 32

33. Mini Project
- Required
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-VHDL code of this Scrambler
-Verify functionality using Modelsim (Waveforms required)
– Second level
-Test Synthesizability using Xilinx ISE
-Utilization Summary from Output Report
• Third level
-Pattern Generated by MATLAB =
- Deadline
– Fourth level
-After Next» Fifth level
session
Session Five 33

34. Summary
• Type declarationedit Master text styles declaration, process declaration
-
Click to is made inside architecture declaration, entity
-
- – Second level
VHDL is a strongly typed language.
Data Types can be classified into:
• Third level
1–Scalar types
2–Composite types
– types
3–User defined Fourth level
» Fifth level
Examples Exercises Labs
18-20 - 4-5
Session Five 34

35. Time for Your Questions
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– Second level
• Third level
– Fourth level
» Fifth level
Session Five 35

36. Download Session 02 Files
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Read Session- 2 Examples carefully to be ready for the next session’s LAB QUIZ
–Lab 06 www.startgroup.weebly.com/vhdl-examples.html
Second level
• Third level
– Fourth level
» Fifth level
Related Sessions
Tutorial 2
Session Five 36

37. Take Your Notes
Print the slides and take your notes here
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38. See You Next Session .. Don’t miss
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Thank
– Second level
• Third level
– Fourth level
You
» Fifth level