The document proposes accelerating XML parsing through prefetching techniques. It discusses how XML parsing consists of character conversion, lexical analysis, and syntactic analysis, which introduces significant overhead. It then presents different prefetching techniques that could be applied to bridge the speed gap between CPU and memory and reduce cache misses. Evaluation shows these techniques can reduce cache misses by up to 80% and improve performance by up to 20%, as well as provide 12.77% energy savings for XML parsing.

1. Acceleration of XML
Parsing through Prefetching
IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 8, AUGUST
2013
Authors: Jie Tang, Student Member, IEEE, Shaoshan Liu, Chen Liu,
Member, IEEE, Zhimin Gu, and Jean-Luc Gaudiot, Fellow, IEEE
Presented By :
Rohit Deshpande
Mtech CSE 2nd sem
130913016
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2. Contents
• Introduction
• Motivation
• The XML Parsing Process
• Prefetching Techniques
• Methodology
• Performance Analysis of XML Parsing
• Memory-Side Acceleration
• Implementation Feasibility
• A Exemplary Hardware Implementation
• Conclusion
• Future Work
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3. Introduction
• Extensible Markup Language (XML) has become a
widely adopted standard for data representation
and exchange.
• Neutrality, Application independency and
Flexibility.
• Morgan Stanley’s Financial Services system,
spends 40% execution time on processing XML
documents.
• This paper proposes to accelerate XML parsing
from the memory side.
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4. Motivation
• XML is widely adopted standard for data
representation and exchange.
• Parsing of XML data introduce significant
overhead.
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5. The XML Parsing Process
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6. • XML data parsing consists of three steps:
• Character conversion
• Lexical analysis
• Syntactic analysis.
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7. XML Parsing Modeling
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8. • Event Driven Parser
• Tree-Based Parser
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9. Prefetching Techniques
• Data prefetching has been proposed as a
speculative technique to bridge the speed gap
between CPU and memory subsystem.
• Classic Prefetching Techniques:-
• Sequential Prefetching
• Stride Prefetching
• Strem Prefetching
• Correlating Prefetching
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10. Overview of Hardware Prefetching
• System Integration of Hardware Prefetcher
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11. Architecture of Hardware Prefetcher
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12. Methodology
• XML Parsers and Benchmarks
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13. • Performance and memory Modeling
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14. Native versus Managed Execution
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15. Performance Analysis Of XML Parsing
• Data Flow of XML Parsing
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16. • Disk Data Loading
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17. Data Loading from Memory Side
• Data flow starting from main memory, going
through each cache layer and finally fetched in
to CPU.
• The CPI of speed test is 0.80.
• Using the SAX parser, the CPI of standard is
1.27, which introduces 58.75 % of overhead.
• Using the DOM parser, the CPI of standard
becomes 1.42, which introduces 77.5% of
overhead.
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18. Memory-Side Acceleration
• Prefetchers
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19. • Performance Analysis
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20. • Performance Improvement for SAX Parsing
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21. • Performance Improvement for DOM Parsing
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22. Implementation Feasibility
• Bandwidth Utilization
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23. • Hardware Cost and Energy Consumption
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25. • Energy Consumption of SAX Parsing
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26. • Energy Consumption of DOM Parsing
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27. A Exemplary Hardware
Implementation
• Power consumption of the prefetcher on FPGA
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28. • Hardware Cost and Power Consumption
Comparison between eMIPS and Prefetcher
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29. Performance comparison of L2-only versus
two-level prefetcher
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30. consumption comparison of L2-only
versus two-level prefetcher
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31. Conclusion
• Authors Proposed to make acceleration for
XML parsing from memory side by improving
its data loading performance.
• Reduce cache misses by up to 80 percent,
which translates into up to 20 percent of
performance improvement.
• 12.77 percent of energy saving.
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32. Future Work
• The ultimate goal is to built a many core chip
in which one core perform conventional
general computing workloads and the other
cores do XML parsing and Garbage Collection.
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33. References
• K. Chiu, M. Govindaraju, and R. Bramley, “Investigating the Limits of Soap Performance for Scientific
Computing,” Proc. IEEE 11th Int’l Symp. High Performance Distributed Computing (HPDC-11), 2002.
• M.R. Head, M. Govindaraju, R. van Engelen, and W. Zhang, “Grid Scheduling and Protocols-
Benchmarking xml Processors for Applications in Grid Web Services,” Proc. ACM/IEEE Conf.
Supercomputing (SC ’06), p. 121, 2006.
• P. Apparao et al., “Architectural Characterization of an XML-Centric Commercial Server Workload,”
Proc. 33rd Int’l Conf. Parallel Processing, 2004.
• P. Apparao and M. Bhat, “A Detailed Look at the Characteristics of xml Parsing,” Proc. First
Workshop Building Block Engine Architectures for Computers and Networks (BEACON ’04), 2004.
• M. Nicola and J. John, “XML Parsing: A Threat to Database Performance,” Proc. 12th Int’l Conf.
Information and Knowledge Management, 2003.
• Int’l HapMap Project: http://hapmap.ncbi.nlm.nih.gov/, 2013.
SAX Parsing Model: http://sax.sourceforge.net, 2013.
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34. • W3C, “Document Object Model (DOM) Level 2 Core Specifica-tion,” http://www.w3.org/TR/DOM-Level-2-Core,
2013.
• K. Chiu, T. Devadithya, W. Lu, and A. Slominski, “A Binary XML for Scientific Applications,” Proc. First Int’l Conf. e-
Science and Grid Computing, 2005.
• XimpleWare, “VTD-XML: The Future of XML Processing,” http://vtdxml. sourceforge.net, Accessed 10, Mar. 2007.
W. Lu, K. Chiu, and Y. Pan, “A Parallel Approach to XML Parsing,” Proc. IEEE/ACM Seventh Int’l Conf. Grid
Computing, Sept. 2006.
• M.R. Head and M. Govindaraju, “Approaching a Parallelized XML Parser Optimized for Multi-Core Processor,” Proc.
Workshop Service-Oriented Computing Performance: Aspects, Issues, and Ap-proaches (SOCP ’07), June 2007.
• R.D. Cameron, K.S. Herdy, and D. Lin, “High Performance XML Parsing Using Parallel Bit Stream Technology,” Proc.
Conf. Center for Advanced Studies on Collaborative Research, Oct. 2008.
• L. Zhao and L. Bhuyan, “Performance Evaluation and Accelera-tion for XML Data Parsing,” Proc. Ninth Workshop
Computer Architecture Evaluation Using Commercial Workloads, 2006.
• J. Moscola and J.W. Lockwood, “Reconfigurable Content-Based Router Using Hardware-Accelerated Language
Parser,” ACM Trans. Design Automation of Electronic Systems, vol. 13, article 28, 2008.
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35. THANK YOU
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