Interrupts, Computer Architecture

1. Explanation
Interrupts
System Interconnections

2. Interrupts
A computer system must provide a method for allowing
mechanisms to interrupt the normal processing.
Interrupts improve processor efficiency
Most external devices are much slower than the processor and
‘busy waiting’ takes up too many resources.
Examples:
External interrupts:
Timing device, Circuit monitoring the power supply, I/O device
requesting data or completed data transfer etc. Timeout errors.
Internal interrupts (caused by an exception condition).
Illegal use of an instruction or data (traps)
example: register overflow, attempt to divide by zero, invalid op code,
stack overflow etcTimer: OS system can perform operations on a regular
basis.
Software Interrupts – Special call instruction that behaves like an interrupt.

3. WRITE
1
WRITE
WRITE
I/O Command
4
END
5
WRITE
1
WRITE
WRITE
I/O Command
4
END
Interrupt Handler
2
3
3a
2a
2b
5
3b
1 4 5 2 4 5 3
1 4 5 2b 4
2a 5 3b
3a
1 4 5 4
2 5
3
No Interrupts
Interrupts -Short I/O wait.
Interrupts -Long I/O wait. (More realistic!)
No Interrupts Interrupts -Short I/O wait.
Short I/O – the I/O
operation is completed
within the time it takes
to execute instructions
in the program that
occur before the next
I/O command. The
processor is kept busy
the whole time.
Long I/O - The ‘next’
I/O command comes
before first I/O has
completed. Processor
still needs to wait.
Some time is saved !
Benefits of Interrupts

4. An example
Busy Wait:
Consider a computer that can execute two instructions
that read the status register and check the flag in 1 µs.
Input device transfers data at an average rate of 100 bytes
per second – equivalent to one byte every 10,000 µs.
The CPU will check the flag 10,000 times between each
transfer.
Interrupt Driven:
CPU could use this time to perform other useful
processing.

5. Interrupt Cycle
The interrupt cycle is added to the instruction cycle.
Processor checks for interrupt indicated by an interrupt flag.
If there is NO interrupt  Fetch next instruction
If there is an interrupt:
Suspend operation of the program
Save its context
Set PC to start address of the interrupt handler
Process the interrupt
Restore the context of the original program and continue its execution.

6. Instruction Cycle with Interrupts
Following each execute cycle:
Check for interrupts
Handle active interrupts

7. Instruction Cycle with Interrupts
Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt
Interrupts remain pending and are checked after first interrupt has been
processed
Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts
When higher priority interrupt has been processed, processor returns
to previous interrupt

8. Handling Multiple Interrupts
Sequential approach – once an
interrupt handler has been
started it runs to completion
(+) Simpler
(-) Does not handle priority interrupts well
Example: Incoming data might be lost.
Nested approach – a higher priority
device can interrupt a lower
priority one.
(+) More complex
(-) Interrupts get handled in
order of priority.

9. Priority Interrupts
Polling
• One common branch address for all interrupts.
• Interrupt sources polled in priority sequence.
• If an interrupt signal is ‘on’, control branches to a service routine for
this source.
• (-) Time overhead to handle many interrupts can be excessive.
• The operation can be sped up with a hardware priority-interrupt unit.
Daisy-Chain Priority
• Hardware solution
• Serial connection of all devices that request interrupts.
• Device with the highest priority takes first position, 2nd
highest takes
2nd
position etc.
• Interrupt request line shared by all devices.

10. Daisy-chain Priority Interrupt
A Serial Approach
CPU
Device 1 Device 2 Device 3
PI P0 PI PI
P0 P0
INT
INTACK
Interrupt Request
Interrupt Acknowledge
Processor data bus
VAD 1 VAD 2 VAD 3

11. One stage of the daisy-chain Priority Arrangement
PI RF PO Enable
0 0 0 0
0 1 0 0
1 0 1 0
1 1 0 1
S
R
Q
Vector Address
Delay
.
. .
Priority In
PI
Interrupt
request
from
device
Open-collector
inverter
Interrupt request
to CPU
Priority Out
PO
RF
From: Computer System Architecture, Morris Mano

12. Parallel Priority Interrupt
Uses a register – whose bits are set separately by the interrupt
signal from each device.
Priority established according to the position of bits in the
interrupt register.
A mask register is used to control the status of each interrupt
request. Mask bits set programmatically.
Priority encoder generates low order bits of the VAD, which
is transferred to the CPU.
Encoder sets an interrupt status flip-flop IST whenever a non-
masked interrupt occurs.
Interrupt enable flip-flop provides overall control over the
interrupt system.

13. Parallel Priority Interrupt Hardware
0
1
2
3
I0
I1
I2
I3
Priority
Encoder
0
1
2
3
y
x
0
0
0
0
0
0
IST
IEN
Disk
Printer
Reader
Keyboard
Enable
Interrupt to CPU
INTACK from CPU
Interrupt
Register
Mask
Register
From:
Computer
System
Architecture,
Morris
Mano

14. Priority Encoder
Circuit that implements the priority function.
Logic – if two or more inputs arrive at the same time, the input
having the highest priority will take precedence.
Boolean functions
X = I’0I’1 Y = I’0I1 + I’0I’2 IST = I0 + I1 + I2 + I3
Inputs Outputs
I0 I1 I2 I3 d Y IST
1 d d d 0 0 1
0 1 d d 0 1 1
0 0 1 d 1 0 1
0 0 0 1 1 1 1
0 0 0 0 d d 0