The document discusses the steps in the logic synthesis process from RTL to optimized gate-level netlist. It includes: 1) RTL description is converted to an internal representation 2) Logic is optimized to remove redundancy 3) Technology mapping implements the representation using cells from a technology library The document also discusses floor planning, which determines routing areas by placing blocks/macros, and placement which places standard cells in rows to minimize area and interconnect cost.

2. inputs and outputs of synthesis:-

3. Synthesis flow : RTL to Gates

4.  logic synthesis def:-
its nothing but converting the RTL(register transfer language) code in to
optimized GATED LEVEL NETLIST

5. Elaborate
Cmd: elaborate
Analyze
Cmd: analyze
HDL
source
file
Translated to
GTECH
Check for syntactical
errors and creates
HDL library objects
Read the
design
Design compiler
Reading design:-

6. Steps in synthesis:-

7. Stage in Synthesis flow
 RTL description :
the designer describes the design at a high level by using RTL constructs.
 translation :
the RTL description is converted by the logic synthesis tool to an unoptimized, intermediate, internal
representation.
 logic optimization :
the logic is now optimized to remove redundant logic. various technology independent Boolean logic
optimization techniques are used.
 technology mapping and optimization :
in this step, the synthesis tool takes the internal representation and implements the representation in gates,
using the cells provided in the technology library

8. Technology library : the technology library contains library cells provided by abc inc. the term
standard cell library and the term technology library are identical and are used interchangeably.
Design constraints : design constraints typically include the following:
Timing-
the circuit must meet certain timing requirements. An internal static timing analyzer checks timing.
Area-
The area of the final layout must not exceed a limit.
Power-
the power dissipation in the circuit must not exceed a threshold.

9. Optimization:-

10. 1.Duplication:- 2.ungrouping:-
3.Resizing:-

11. Compile strategy:-
 We can use three types of compilation strategies for the
hierarchical
Designs.
 Top_bottom compile
 Bottom_top compile
 Mixed compile

13. Floor plan def:-
A floor planning is the process of placing blocks/macros in the chip/core area,
thereby determining the routing areas between them.

14. Netlist
.v
.SDC
.lib
TLU+
files Floor plan
control
parameters
Floor plan
Die/Block area I/O pad/placed Macro placed Power grid design
Power pre-
routing
Standard
cell
placement
areas
Inputs &outputs:-

15. 2.Pin assignment 3.Macro placement1.Die area& core area 4.Blockage creation
5.Power rings 6.Power strips 7.Physical cells 8. Special route

16. Floor plan constraints:-
 Minimize the total chip area.
 •Make routing phase easy (routable).
 •Improve the performance by reducing signal delays.

18. Placement def:-
Placement is the process of placing standard cells in the rows created at floor planning stage. The
goal is to minimize the total area and interconnects cost. The quality of routing is highly determined
by the placemen

19. Inputs &outputs:-

20. Checklist after placement:-
 Timing
 Congestion
 utilization