Automated layout synthesis tool for op amp

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Automated Layout Synthesis Tool for Op-Amp
1
Nueraimaiti Aimaier (Nurahmad Omar) GS 34530 mknurahmat@gmail.com Electrica...

Op-amp Physical Design Background
2

Stick Representation
3 d
d
d
s
s
1
2
3
4
1
2
1
2
3
2
3 4
3
4
M1
M2
M3
Same width
Source: F.Malobert...

Layout Oriented Design
4
Possible stacks: 1 p-channel, 2 n-channel
M3, M4, M6
M1, M2
M5, M7
Source: F.Maloberti – La...

Stack Design and Interconnections 5
Source: F.Maloberti – Layout of Analog CMOS IC

Layout Template of Op- Amp
6
Load (Pmos)
Differential Pair (Nmos)
Bias (Nmos)

Differential Pair
7
A
A
A
A
B
B
B
B
M1 M2 A
A
B
B
M1 M2

Bias
8
C
C
A
A
B
B
C
C
Current Mirror
M5 M8 C
A
A
B
B
C

Load
9 C
C
A
A
B
B
C
C C
C
C
C
Current Mirror
M3 M4

Design Flow Chart
10
schematic netlist
Partitioning
matching generator
(Common-centroid)
auto routing
Placement &
...

11
The whole process of the design flow consists of four main components, which are Partitioning, Matching generator, Pla...

12
Placement & Floorplanning: After partioning and matching generator, this step locate each transistor according to com...

Process algorithm
13
Algorithm Begin 1 import schematic; 2 while not (stopProcess);
3generate netlist;
4get netlist in...

Detail in each process Netlist
MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1
*
X_M6 OUT N$39 VD...

Constraints 16 Matching constraints:
M1, M2 ----- Differential pair
M3, M4 ----- Current mirrors
M5, M8 ----- Curren...

Partitioning
17
Pmos
Nmos
Nmos

File format
Output:
Array
V1= (M6, M9, M4, M3) # Pmos
V2=(M1,M2) # Nmos
V3=(M7, M8, M5) # Nmos
18

19
Partitioning
INPUT
Netlist
consraints
Vertex V1
load (pmos)
Vertex V2 differential Pair(nmos)
Vertex V3
Bias (...

Partitioning process algorithm
20
Algorithm Begin
1get netlist info;
2 while (partitioning) 3 foreach (transistor) 4 c...

Algorithm Workout
21
differential pair
(Constraint)
Vertex V2 pmos Vertex V1 nmos Vertex V3
E.g. V1= (M6, M9, M4, M3)...

Partitioning snapshot
22
Vertex V1
pmos
Vertex V2 nmos
Vertex V3
nmos

Condition/range 23
The op-amp should be conventional two-stage amplifier OTA ( Operational Transconductance Amplifier), ...

Matching generator Matching generator
INPUT 1. Netlist (finger-numbers) 2. Constraints
M3 M4… M6 M6 M6 … (V1A)
M4 M3… M...

Matching process algorithm
25
Algorithm Begin 1 get netlist info; # multi-finger info e.g. M=8 means 8 multifinger 2 whi...

26 14 choose pmos V1; 15 choose current mirror;
16 repeat step 5 to 13 to get V1A and V1B;
17 add M/2 numbers of remaini...

File format
27 Matching generator
Array V1A= (M3,M4…M6,M6,M6…) OR V1A= (M3,M4,M4,M3…M6,M6,M6…) V1B= (M4,M3…M6,M6,M6…) O...

Matching generator snapshot
28 Load Differential Pair Bias

Condition/Range
29
The differential pair and common-centroid transistors are given by the user
The numbers of multi-f...

Placement & Floorplanning
30
Placement & Floorplanning INPUT 1. Netlist 2. DRC file

Placement&Floorplanning process algorithm
31 Algorithm Begin
1get netlist info; 2 get DRC info; 3 while (placement) 4 fo...

32
A
A A A
B
B B B
C
A C B
C
C A A
B
B C C
C
C C A
C
B C C
Track Size *
Number Of Tracks
Distance(block1...

Placement Snapshot 33

34
Placement file format ( for each sub-block)
Array V1A= (…M6,M6,M3,M4,M6,M6…) V1B= (…M6,M6,M4,M3,M6,M6…) V2A= (…M1,M2...

Routing 35
Placement &
Floorplanning INPUT 1. Netlist 2. DRC file OUTPUT
1.Transisors D,G,S coordinate locations
2.Hor...

36 A A
A
A B B
B
B A C
B C C A
A
B B C
C C C A
C
B C C
Routing channel
Routing channel Routing channel C
C
R...

File format 37
Matrix
X_M6
X_M9
X_M4
X_M3
X_M7
X_M8
X_M5
X_M2
X_M1
Drain Gate Source 1 2 3 4 4 3 2 5 3 5 5 3 1...

Channel routing
FZR Rev 1.0 38
Can be implemented between each blocks and each row inside the block.

Routing algorithm process
39
Horizontal Constraints: This exist when the set of columns spanned by two nets Intersect, ...

3a. For j=2 to n do
Assign net ij to an arbitrary available track tj.
4.Once, the horizontal tracks are assigned, the ve...

Routing snapshot 41

Condition/Range
42
 Channel routing have enough space
 Limited metal layer ( two layer)

Result
43
Detail of the software tool:
Reading DRC file
Reading netlist
Partitioning algorithm
Matching algorith...

Running the program 44

Load (Block1)
45

Differential pair (Block2)
46

Bias (Block3)
47

Netlist 1  Layout 48
* MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1
*
CC N$39 OUT 3P
X_M6 OU...

FZR Rev 1.0 49
Netlist 1 corresponding layout

Netlist 2  Layout
* MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1
*
CC N$39 OUT 3P
X_M6 OUT N...

FZR Rev 1.0
51
Layout works correctly, but the VDD and VSS metal layer did not change location correspondly, waste area.

Block1(Pmos) error
FZR Rev 1.0
52
The poly disconnected below 2nd row get

Netlist 3  Layout
* MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1
*
CC N$39 OUT 3P
X_M6 OUT N...

54
Layout works correctly, but the VDD and VSS metal layer did not change location correspondly, waste area.

Netlist 4  layout
FZR Rev 1.0 55
* MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1
*
CC N$39 OU...

FZR Rev 1.0 56
Multi-finger numbers change, placement works correctly with symmetry layout, but routing does not work co...

DRC Check
57

Assumption & Design issue 58
i.Condition/range of the tool:
Two-stage OTA (Operational Transconductance Amplifier)
Th...

Conclusion & Future work 59
•In this project, we presented a layout method for operational amplifier. Our analog placer c...

Milestone
60
Week
Topic
1
Unix
2
Unix & Shell Programming
3
Perl
4
SoC design automation review
5
SoC design ...

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