The document provides a comprehensive overview of computer arithmetic, which encompasses the design of efficient circuits for various arithmetic operations, including addition, subtraction, multiplication, and division. It discusses the implementation of arithmetic units in hardware, the importance of binary over decimal representation, and the functionality of algorithms and components such as the Arithmetic Logic Unit (ALU). Additionally, it covers floating-point operations and the handling of overflow conditions in computing.

1. COMPUTER
ARITHMETICS
Computer Organization and Architecture
SURYA KUMAR SAHANI SURAJ KUMAR
2K19/CO/399 2K19/CO/396
LET'S EXPLORE

2. “ Is a subfield of digital computer organization …
deals with the hardware realization of arithmetic
functions … a major thrust <of which> is the design
of hardware algorithms and circuits to enhance the
speed of numeric operations.” -- Parhami
“ Encompasses the study of number representation,
algorithms for operations on numbers,
implementations of arithmetic units in hardware, and
their use …” --Ercegovac & Lang
COMPUTER ARITHMETICS
Computer Organization and Architecture

3. What Is Computer
Arithmetic?
Design of efficient circuits for
arithmetic operations (+, -, x, /,
sqrt, log, sine, …)
Numerical methods for solving
systems of equations
Algorithm
Accuracy
Speed/power/area/ reliability trade-offs
Test/verification
Computer Organization and Architecture
Hardware Software Issues

4. Applications
General purpose systems
Fast primitive operations for
processor data paths
Special purpose systems
Signal and image processing
Special purpose systems
Information on applications of
RNS arithmetic in signal
processing
Special purpose systems
Real-time 3D graphics
Special purpose systems
Network processors (data
compression,
encryption/decryption)
Special purpose systems
HDTV, image compression

5. Title of the Report | Date of the Report
Contents
Introduction
Addition and Subtraction
Multiplication Algorithms
Division Algorithms
Floating-point Arithmetic operations
Decimal Arithmetic Unit
Decimal Arithmetic operations

6. Title of the Report | Date of the Report
INTRODUCTION
Arithmetic instructions in digital computers manipulate data to produce results necessary for the solutions of
computational problems. These instructions perform arithmetic calculations and are responsible for the bulk
of activity involved in processing data in a computer. • The four basic arithmetic operations are addition,
subtraction, multiplication and division. • From these four basic operations , it is possible to formulate other
arithmetic functions and solve problems by means of numerical analysis methods. • An arithmetic processor
is the pat of a processor unit that executes arithmetic operations. • An arithmetic instruction may specify
binary or decimal data, and in each case the data may be in fixed-point or floating point form. • Negative
numbers may be in signed magnitude or signed compliment representation. • Fixed point numbers may
represents integers or fractions.

7. Reasons for using Binary over Decimal
in Computer Arithmetics
Computers were built with basic electronic components called transistors, which were simple switches
that had two states, OFF and ON. It was very easy to represent 0 by OFF and 1 by ON. We can build
more complex basic components for our computer with more states, but that will cost us more money.
For instance we can create a decimal component with 10 states, but it will probably cost us more than
10 times as much as a binary circuit with 2 states.
Wecan represent any number from 0 to 15 with four binary digits, and that will cost us only 4 times as much as one binary digit. They quickly realized that they could represent any number just as easily with binary
arithmetic as with decimal arithmetic. Since accountants often preferred decimal arithmetic to binary arithmetic, they invented binary coded decimal (BCD) which represented decimal numbers as four binary bits. Thus
0 = 0000, 1 = 0001, 2 = 0010, 3 = 0011, and so on up to 9 = 1001. They had 6 more BCD digits left over to represent things like positive and negative signs. For instance, 1100 might represent positive and 1101
negative.
Title of the Report | Date of the Report

8. Arithmetic Logic
Unit
The ALU is a fundamental component of all processors,
the design and function of an ALU may vary between
different processor models. For example, some ALUs
only perform integer calculations, while others are
designed to handle floating point operations as well.
Some processors contain a single ALU, while others
include several arithmetic logic units that work together
to perform calculations. Regardless of the way an ALU is
designed, its primary job is to handle integer operations.
Therefore, a computer's integer performance is tied
directly to the processing speed of the ALU.
Computer Organization and Architecture

9. Addition &
Subtraction
Computer Organization and Architecture

10. GENERAL CONCEPT
Decimal
addition
(carry) 1_
19
+ 7
___
26
Binary addition
( carry) 111_
10011
+ 111
_____
11010

11. REALIZATION
Simplest solution is a battery of full adders.

12. OBSERVATIONS
•Adder add four-bit values
•Output c4 indicates if there is an overflow
–A result that cannot be represented using 4 bits
–Happens when A+ B > 15
•Operation is slowed down by carry propagation

13. SIGNED AND UNSIGNED ADDITIONS
Unsigned addition in
4-bit arithmetic
( carry) 11_
1011
+ 0011
_____
1110
11 + 3 = 14
(8 + 4 + 2)
Signed addition
in
4-bit arithmetic
( carry) 11_
1011
+ 0011
_____
1110
-5 + 3 = -2
• Same rules apply even though bit strings represent different values
• Sole difference is overflow handling

14. OVERFLOW HANDLING { I }
•No overflow in signed
arithmetic
( carry) 111_
1110
+ 0011
______
0001
-2 + 3 = 1
(correct)
Signed addition in
4-bit arithmetic
( carry) 1__
0110
+ 0011
______
1001
6 + 3 != -7
(false)

15. OVERFLOW HANDLING { II }
n signed arithmetic an overflow happens when
• The sum of two positive numbers exceeds the maximum positive
value that can be represented using n bits: (2^(n – 1) – 1)
• The sum of two negative numbers falls below the minimum negative
value that can be represented using n bits: ((– 2)^n – 1 )

16. EXAMPLE
• Sixteen possible values
• Positive overflow happens when result > 7
• Negative overflow happens when result < -
8
•
•
>
•
<

17. OVERFLOW HANDLING { III }
- Ignores unsigned overflows
• Implements modulo 2n arithmetic
- Generates an interrupt whenever it detects a signed overflows
• Lets the OS handled the condition

18. SUBTRACTION
Can be implementing by
• Specific hardware
• Negating the
subtrahend
- Toggle all bits then add
one

19. IN 4-BIT ARITHMETIC

20. ADD : X <- X + Y SUB : X <- X - Y
HARDWARE
IMPLEMENTATION

21. Multiplication
Title of the Report | Date of the Report

22. Multiplication Algorithms
Multiplication of two fixed point binary numbers in signed
magnitude representation is done with paper and pencil of
successive shift and add operation.
Computer Arithmetics
if the multiplier bit is a 1,the multiplicand is copied down;
otherwise zero are copied down.

23. Hardware Implementation for Signed-Magnitude data
Hardware Implementation for Signed-Magnitude data When multiplication is implemented in a digital computer, it is
convenient to change the process slightly. First instead of providing register to store and add simultaneously as
many binary numbers as there are bits in the multiplier , as it is convenient to provide an adder for the summation of
only two binary numbers and successively accumulate the partial products in a register. Second instead of shifting
the multiplicand to the left , the partial product is shifted to the right.
The hardware for multiplication consists of the equipment , plus two are more registers
These registers are together with registers A and B..
The multiplier stored in the Q register and its sign in Qs. The sequence counter SC is initially set to a number equal to
the number of bits in the multiplier. The counter is decremented by 1 after forming each partial product
The sum of A and B forms a partial product which is transferred to the EA register .
Computer Arithmetics

24. The shift will be denoted by the statement shr EAQ to designate the right shift depicted .
The least significant bit of A is shifted into the most significant position of Q.
Computer Arithmetics

25. This figure is a flowchart of the hardware multiply
algorithm.. Initially the multiplicand is in B and the
multiplier in Q there corresponding signs are in Bs and Qs
.,respectively. Register A and E are cleared and the
sequence counter SC is set to a number equal to the
number of bits of the multiplier. After the initialization ,
the low order bit of the multiplier is in Qn is tested .if it is
1,the multiplicand In B is added to the present partial
product in A . If it is 0, nothing is done . Register EAQ
shifted once to the right to form the new partial product.
The process stops when SC=0. Note that the partial
product formed in A is shifted into Q one bit at a time and
eventually replaces multiplier. The final product is
available in both A and Q,with A holding the most
significant bits and Q holding the least significant bits.
Hardware Algorithm
Computer Arithmetics

26. Booth Multiplication Algorithm
Booth Algorithm gives a procedure for multiplying binary integers in
signed-2’s compliment representation
Computer Arithmetics

27. Booth
Multiplication
Algorithm
Booth Algorithm gives a
procedure for multiplying
binary integers in signed-
2’s compliment
representation .
Computer Arithmetics

28. Booth algorithm for
multiplication of signed-2’s
compliment
The two bits of multiplier in Qn and Qn+1 are
inspected . If the two bits are equal to 10 it
means that the first 1 in a string of 1’s has been
encountered The final value of Qn+1 is the
original sign bit of the multiplier and should not
be taken as part of the product

29. Array Multiplier
The multiplication of the two binary numbers
can be done with one micro-operation by
means of a combinational circuit that forms
the product bits all at once. This is a fast way
of multiplying two numbers since all it takes is
the time for the signals to propagate through
the gate that form the multiplication array.
Computer Arithmetics

30. A 2-bit by 2-bit array multiplier

31. Division
Computer Arithmetics

32. Division Algorithms
Division of two fixed-point binary numbers in signed
magnitude representation is done with paper and
pencil by a process of successive compare ,shift ,and
subtract operations .. Hardware implantation of signed
magnitude data
Example of Binary division
Computer Arithmetics

33. Example of binary division with digital
hardware Instead of shifting the divisor to
the right, the dividend or partial remainder,
is shifted to the left, thus leaving the two
numbers in the required relative position,
subtraction may be achieved by adding A
to the 2’s compliment of B. EAQ is shifted
to the left with 0 instead of Qn and the
previous value of E lost. The divisor is
stored in the B register and the double
length dividend is stored in register A and
Q The information about relative
magnitude is available in E. if E=1,it
signifies that A ≥B. A quotient bit 1 is
inserted into Qn and the partial remainder
is shifted left to repeat the process. If E=0,
it signifies that A<B so the quotient in Qn
remains a 0. The sign of the remainder is
the same as the sign of the dividend .

34. This occurs because any dividend will be greater than or equal to
zero.
Over flow condition is usually detected when a special flip-flop is set.
Which will call it a divide overflow flip-flop and label it DVF
The occurrence of a divide overflow can be handled in variety of ways
.
In some computers it is the responsibility of the programmers to
check if DVF is set after each divide instruction
The occurrence of a divide overflow stopped the computer and this
condition was referred to as a DIVIDE STOP.
The best way to avoid a divide overflow is to use floating point data.
The divide overflow can be handled very simply if numbers are in
floating point representation.
Divide overflow

35. The dividend is in A and Q and the divisor
in B. The sign of the results transferred
into Qs to be part of quotient. A divide
overflow condition is tested by subtracting
divisor in B from half of the bits of the
dividend stored in A. if A≥B, the divide
overflow flip-flop DVF set and the
operation is terminated prematurely. By
doing the process as shown in the
flowchart the quotient magnitude is
formed in register Q and the remainder is
found in the register A. The quotient sign is
in Qs and the sign of the remainder in As is
the same as the original sign of the
dividend.
Hardware algorithm

36. Floating
Point
Operations
Computer Organization and Architecture

37. FLOATING POINT NUMBERS
•
• Very similar to scientific notation
- 3.5×106, 0.82×10–5,75×106, …
• Both decimal numbers in scientific notation and floating point numbers can be normalized:
- 3.5×106, 8.2×10–6,7.5×107, …

38. NORMALIZING BINARY NUMBERS
• × ^
( )
• 0.01 becomes 1.0×2^(-2)
• 0.11 becomes 1.1×2^(-1)
• 1.1 is already normalized and equal to1.0×2^0
• 10.01 becomes 1.001×2^1
REPRESENTATION
• Sign + exponent + coefficient
• Sign :- 0 for positive number & 1 for negative number

39. GUARD BITS
•
• We eliminate the possibility of overflow by appending the
appropriate number of guard bits to a binary word. For a
two's complement signed value, the guard bits are filled
with either 0's or 1's depending on the value of the most
significant bit (MSB).

40. Floating
Point Addition
& Subtraction
Computer Organization and Architecture

41. DECIMAL FLOATING POINT ADDITION (I)
• × ^ + × ^ =
• Denormalize number with smaller exponent:
• 5.25×10^3 + 0.122×10^3
• Add the numbers:
• 5.25×10^3 + 0.122×10^3 = 5.372×10^3
• Result is normalized

42. DECIMAL FLOATING POINT ADDITION (II)
• × ^ + × ^ =
• Denormalize number with smaller exponent:
• 9.25×10^3 + 0.822×10^3
• Add the numbers:
• 9.25×10^3 + 0.822×10^3 = 10.072×10^3
• Normalize the result:
• 10.072×10^3 = 1.0072×10^4

43. BINARY FLOATING POINT ADDITION (I)
• + × ^ + × ^
• Denormalize number with smaller exponent:
• 1.001×2^3 + 0.01×2^3
• Add the numbers:
• 1.001×2^3 + 0.01×2^3 = 1.011×2^3
• Result is normalized

44. BINARY FLOATING POINT SUBTRACTION
• × ^ × ^
• Denormalize number with smaller exponent:
• 1.01×2^2 – 0.11×2^2
• Perform the subtraction:
• 1.01×2^2 – 0.11×2^2 = 0.10×2^2
• Normalize the results
• 0.10×2^2 = 1.0×2^1

45. Floating
Point
Multiplication
Computer Organization and Architecture

46. DECIMAL FLOATING POINT
MULTIPLICATION
•
• Coefficient of product is the product of the coefficients of multiplicand and multiplier
• Compute sign using usual rules of arithmetic
• May have to renormalize the product

47. DECIMAL FLOATING POINT
MULTIPLICATION
• × × × =
• Exponent of product is:
• 3 + 2 = 5
• Multiply the coefficients:
• 6 ×2.5 = 15
• Result will be positive
• Normalize the result:
• 15×105 = 1.5×106

48. BINARY FLOATING POINT
MULTIPLICATION
•
• Coefficient of product is the product of the coefficients of multiplicand and multiplier
• Compute sign using usual rules of arithmetic
• May have to renormalize the product

49. BINARY FLOATING POINT
MULTIPLICATION
• × × × ×
• Exponent of product is:
• 2 + 1 = 3
• Multiply the coefficients:
• 1.1 × 1.1 = 10.01
• Result will be positive
• Normalize the result:
• 10.01×23 = 1.001×24

50. Thank you!
Ask us if there are any questions. SURAJ KUMAR
2K19/CO/396
SURYA KUMAR SAHANI
2K19/CO/399
Computer Organization and Architecture