Hyper Transport (HT) is an open standard interconnect technology that provides high-bandwidth communication between processors, GPUs, and I/O devices. It was developed to address the growing performance gap between rising processor speeds and slower I/O buses. HT uses low-voltage differential signaling and a packet-based protocol to provide low latency, scalable connections at speeds up to 1.6GHz per channel for aggregate bandwidths over 12.8GB/s. The technology simplifies system design, improves performance, and aims to be compatible with legacy systems while enabling continued improvements.

1. HYPER TRANSPORT TECHNOLOGY BY, U.L.SUJATHA 08Q61A0542

2. AGENDA: INTRODUCTION HISTORY HOW IT WORKS? IMPLEMENTATIONS PROS AND CONS CONCLUSION

3. INTRODUCTION Hyper Transport (HT) is a state-of-art packet-based, high-bandwidth, scalable, low latency point-to-point interconnect technology that links processors to each other, processors to coprocessors and processors to I/O and peripheral controllers. Hyper Transport is an open standard technology managed, promoted and licensed to the industry at large by the Hyper Transport Consortium

4. WHY HTT IS DEVELOPED? THE I/O BANDWIDTH PROBLEM While microprocessor performance continues to double every eighteen months, the performance of the I/O bus architecture has lagged, doubling in performance approximately every three years. Every time processor performance doubles, latency only increases by a factor of 1.2.

5. THE I/O BANDWIDTH PROBLEM

6. THE HYPERTRANSPORT™ TECHNOLOGY SOLUTION HyperTransport is intended to support “in-the-box” connectivity High-speed, high-performance, point-to-point link for interconnecting integrated circuits on a board. Max signaling rate of 1.6 GHz on each wire pair, a HyperTransport technology link can support a peak aggregate bandwidth of 12.8 Gbytes/s.

7. THE HYPERTRANSPORT™ TECHNOLOGY SOLUTION

8. HISTORY:

9. HYPERTRANSPORT™ DESIGN GOALS Improve system performance Simplify system design Increase I/O flexibility Maintain compatibility with legacy systems Ensure extensibility to new system network architecture (SNA) buses Provide highly scalable multiprocessing systems

10. FLEXIBLE I/O ARCHITECTURE The physical layer defines the physical and electrical characteristics of the protocol. This layer interfaces to the physical world and includes data, control, and clock lines. The data link layer includes the initialization and configuration sequence, periodic cyclic redundancy check (CRC), disconnect/reconnect sequence, information packets for flow control and error management, and double word framing for other packets. The protocol layer includes the commands, the virtual channels in which they run, and the ordering rules that govern their flow. The transaction layer uses the elements provided by the protocol layer to perform actions, such as reads and writes. The session layer includes rules for negotiating power management state changes, as well as interrupt and system management activities.

11. DEVICE CONFIGURATIONS

12. ELECTRICAL CONFIGURATION The signaling technology used in HyperTransport technology is a type of low voltage differential signaling (LVDS ). LVDS has been widely used in these types of applications because it requires fewer pins and wires. Cost and power requirements are reduced because the transceivers are built into the controller chips.

13. HYPERTRANSPORT ENVIRONMENTS

14. HYPERTRANSPORT ENVIRONMENTS

16. ADVANTAGES It is a packet based technology Provides low latency High bandwidth Decreases no. of buses Reduces packet overhead

18. CONCLUSION Hyper Transport technology is a new high-speed, high-performance, point-to-point link for integrated circuits. It provides a universal connection designed to reduce the number of buses within the system, provide a high-performance link for embedded applications, and enable highly scalable multiprocessing systems. Doubtlessly future will see the tremendous advancement of Hyper Transport technology. Hyper Transport technology will bring a revolution in the bus architecture.