1. Hash Sorter - Firmware Implementation and an Application for the Fermilab BTeV
Level 1 Trigger System
J. Wu, M. Wang, E. Gottschalk, G. Cancelo and V. Pavlicek,
Fermilab, Oct. 2003
Hash Sorting for Triplet Matching Acceleration
Hash Sorter
The slopes of matching triplets
• Hash sorter logically stores data items (e.g. triplets) into must be approximately equal.
bins derived from a key value (e.g. slope of the triplets).
• Each bin represents a range of the key value. External Triplets Without hash
• Each writing or reading takes one memory access (one sorting, all O(n2)
clock cycle in FPGA implementation). combinations
Triplet Matching must be checked.
Without Hash Sorting
Data Items Internal
Triplets
Hash sorted
Data Items 2000000
Hash sorted External Triplets 1500000
seg_match
seg_match_hash
according to their slopes 1000000
total
Hash Sorter 500000
Triplet Matching 0
0 2 4 6 8 10 12
Hash sorting ~ With Hash Sorting N umb er o f Int er ac t i o n/B eam C ro s s i ng
histogram booking
Hash sorted Internal Triplets Timing Results
+ saving ID’s of the data items.
according to their slopes
With hash sorting, only these
combinations need to be checked.

2. Firmware Implementation of Hash Sorter BTeV Level 1 Pixel Trigger
External Triplets
Internal Triplets
• Internal and external triplets are first
found by the FPGA segment finders.
DIN DOUT
• Triplets data are sent through the switch.
• The nodes of the track/vertex farm match 30 station pixel detector
DATA
RAM
the internal and external triplets to form
tracks for further trigger processes.
FPGA segment finders
BEGIN
COUNT
END The HashBlk Block Switch: sort by crossing number
(+ DATA RAM) track/vertex farm
(~2500 processors)
Index Pointer
RAM RAM
Merge
Trigger decision to
Global Level 1
DSP0 Buffer Manager
InBuff
HashBlk
DSP1
HashBlk
DxBin
DSP3 DSP2
S4STEPS DSPSEL HashBlk Pre-prototype of the
HashBlk Track/Vertex Farm Node
• Triplet data are hash sorted in the
DSP Buffer Manager parasitically.
Silicon Usage: 1% 4 x 1% • The hash sorted data are sent to the
DSP daughter cards.
DSP
Hash Sorter Added to Existing • DSP’s match the internal and external
Buffer Manger (xc2v1000) triplets faster with hash sorted data.

3. BTeV Si Pixel Detector and Its Level 1 Detached Vertex Trigger
B-meson
p p
b
Tracks Detached from Simulated B Event
the Primary Vertex
CZero
BTeV
14,080 pixels (128 rows x 110 cols) sensor module
50 µm Multichip module
1 cm
400 µm
Si pixel sensors 5 cm 128 rows x
22 columns
5 FPIX ROC’s
Fermilab 10 cm
Wire bonds HDI flex circuit
Sensor module
6 cm
Si-Pixel Detector 380,160 pixels
per half-station
total of 23Million pixels Pixel detector half-station
in the full pixel detector Bump bonds
Readout module