Personal Information
Organization / Workplace
San Francisco Bay Area United States
Occupation
ASIC Design Verification Engineer at Marvell Semiconductor
Industry
Electronics / Computer Hardware
About
"The only true wisdom is in knowing you know nothing"
I am a ASIC Design Verification Engineer at Marvell with an ever growing passion for semiconductor engineering.
My skills include:
ASIC Design Flow: RTL Design/Modeling, Logic Synthesis, Digital Design, Static Timing Analysis
Verification methodologies: Assertions & directed tests based verification, Coverage driven verification,UVM basics
Physical/Custom Design: Cadence Virtuoso, Calibre verification tools (LVS/DRC) Circuit Simulation: Spice tools (HSPICE, LT-SPICE), Cadence Spectre, NI-Multisim
Digital CAD Tools: Questa Sim, Altera Modelsim, Quartus Prime, Mentor Modelsim
Programming and scripting: Verilog, VHDL, System Verilog ...
Tags
hspice
memory scheduling
bank first
row first
alu
addition and subtraction unit
ripple carry adder
adders
vhdl
linear carry select adder
full wave rectifier
opamp
leakage power
force directed scheduling
area optimum
dag
technology mapping
cache replication schemes
han carlson
koggestone
brent kung
ladner fischer
prefix adders
computer system design
atalanta
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