1. Hewlett Packard Enterprise India Pvt Ltd.
Building No:02, DLF CYBERGREEN
1st, 4th & 5th Floor, Tower D & E
DLF Cyber City, Phase III
Gurgaon - 122 002
Haryana, India
Issue Date : 13-Jul-2016
To Whom So Ever It May Concern
This is to certify that project entitled Multiplexer Design and its Timing Constraints Analysis,
designed on VLSI VHDL & PCB Design technology is an original work carried out by B.Tech
student Mr. Awnind Abhay Shrivastava, Enrollment ID HPER-5996, of K C C Institute of Tech,
Greater Noida from 14-Jun-2016 to 13-Jul-2016 at HPE Nodal Training Centre,Noida.
The matter embodied in this project is a genuine work done by the student and has not been
submitted to the university or to any other university/institute for the fulfillment of the
requirement of any course of study.
Hope you have found all the above details in order.
Thanking You.
For Hewlett Packard Enterprise
Atanu Sur
(Account Manager)