Kindly share CV's@ suprajalavanya.kethepalli@altran.com

1. We Are Hiring……
Area Experience Skills
DFT Engineer 3-8 years - Chip-levelDFTinsertionwithsoundknowledgeof scan
compression,MBIST& JTAG techniques
- Shouldhave goodpostsilicon DFTbringupanddebugexperience
- Hands onin multi vendorDFTtools
- Create testplanfor complex ASICsanddrive
the DFT implemetation&verification
- Abilitytoguide people,multiplex manyissuesandsetpriorities
- Good communicationandleadershipskills
RTL 3-10Years - RTL IPassemblyknowledge.Understandingof IPXACT aplus.
- Hands onexperienceof codinginVerilogandVHDL.
- Understandingof PowerIntent,Powerestimationandchecks.
- Experience of Designrule checksandClockdomaincrossing
checksusingSpyglassorsimilartool.
- Specificationwriting.
- IP RTL developmentexperience.
- - Good knowledge of versioncontrol toolslike Clearcase
and Designsync.
PD Engineer 3-8+years - Thorough understanding and knowledge of the entire
Back end flow rtl to gdsii
- Must be familiar with Industry standard tools like
ICC/Encounter/Talus/Olympus
- Should have expertise in Timing analysis and closure
- Should have Tcl and perl scripting skills
- Should have work experience in the latest technology
nodes like 16nm/14nm
- Should be familiar with low-power design and their
impact on Back end flow (power switches/Level
shifter/Isolation cell/retention cells/Back
biasing/Forward biasing)
STA Engineer 3-12 years - Shouldhave goodtimingconceptsandable toclose timingof
Block/SoC

2. independently.
- Shouldhave handsonexperience inconstraintgeneration
- Handson experience inLogical synthesislike Designcompiler/
Rc compiler
- KnowledgeinFormal Verification.Comfortablewith
LEC/formalitytools
- Shouldable togenerate andimplementfunctionalEcos
- Shouldhave experience inPre-layoutandPostlayouttiming
analysisintools
- Shouldhave experience intwoindustrystandardtoolslike
Primetime/ETS
- Handson experience incrosstalktimingclosure.
- KnowledgeinPathbasedanalysis,AOCV,DMSA isa plus.
- Knowledgeincompletephysical Designflow isaplus.
Memorydesign
&
Characterization
3-7 years - The candidate will be workinginmemorydesignand
characterization.
- Aspart of the design,the candidate wouldbe involvedin
SRAMor ROM memorydesigneitherfromscratchor as part
of optimizationof the existingdesign.
- The candidate wouldbe workingondesignrobustness
analysis usingappropriate simulationtools.
- He will alsobe workingoncharacterizationof the memory
and generatingfinal timingmodelsforcompilerorfor
memoryinstance.
- Candidate willworkondesignandcharacterizationas
individualcontributoraswell asworkingwiththe team.
Standardcell
Characterization
2-5 years - 3 or more yearof expinstdcell/customlayout
- Shouldhave workedonvirtuosoandcaliberfor
verifications.
Verification 3-15 Expert in UVM/OVM for Verification
• System verilog assertions • Perl • Functional + Code
Coverage

3. • Verilog and VHDL
• Cadence IUS (preferred) or Mentor Questasim
• Image Sensor knowledge is a plus
• Experience with SPI/I2C is a plus
AnalogCircuit
Design
3-7 years  6-10 yearsof relevantexperienceinAnalog&Mixedsignal IO
design.
· Able todefine orinterpretthe requirementsintocircuit
designs.
· ProvenanalogCircuitdesigncompetency,like schematic
generationandsimulationonCadence Tool sets.Worstcase
identification,toplevel simulation,Monte Carloanalysis,and
simulationdataanalysis
· Postlayoutparasiticextractionandsimulation,Toplevel
verification,blocklevelmodeling,toplevelsimulation
· CircuitsincludesLinearAmplifiers,Drivers,Low-dropout
regulators,Charge Pump- Regulators,Bandgapand
Buck/Boostconverters,references,comparators.
· Experience onHighspeedserial/paralleldatalinks(multi
Gb/s),PHY circuits,transceivers,PLLs,ClockandData
Recoverycircuits.
· Verifyperformance requirementsusingappropriate
behavioral modeling,Spice simulation,andverificationtools.
Documentdesignsandpresentreviewstopeers.
· KnowledgeonPhysical Designmethodsandissues.
PV Engineer 3-8+years  Shouldhave goodknowledgeonphysical Designflowsat
Blocklevel /SoClevel
 Shouldhave goodunderstandingonLEF,RoutedDEF
 Shouldhave handson experience onPNRtoolslike
EDI/ICC/Atoptech/Olympus
 Expertincalibre DRC/LVS
 Shouldhave experience inEDA toolslike Calibre andCadence
PVS
 Shouldable todebugLVS/DRCissuesbytracingroutednetsin
PNRtools
 Shouldhave workexperience inthe latesttechnologynodes
like 16nm/14nm
 Shouldhave Tcl and perl scriptingskills
 Shouldbe familiarwithlow-powerdesign(power

4. switches/Levelshifter/Isolationcell/retentioncells/Back
biasing/Forwardbiasing)
FPGA 3-10Years - Expertise inFPGA/SOPCImplementations
- End-to-EndFPGA/SystemDevelopment
- Expertise inXilinx/AlteraFPGA Implementationflow
- Logic Estimation
- FPGA Selection