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PARTHAGEETSAMANTARAY
S/OMr. PatitapabanSamantaray
Ray Bahadur Lane,Balagandi,
Puri – 752001 Contact No:+91-8884299705
Odisha Mail ID: pgsmntry@hotmail.com
CAREER OBJECTIVE:
To acquire a challengingpositionwhere Ican implementmyknowledge andskill andcontributeto
organisational growth.
EDUCATIONAL QUALIFICATION:
 B.Tech in ELECTRONICS AND COMMUNICATIONENGINEERING fromNational Institute of
Science and Technology,BerhampurunderBPUT witha CGPA of 8.06
 Class XII fromB.JB. JUNIORCOLLEGE, BhubaneswarunderCHSE-OdishaBoardin2011 with
79.5%
 CLASS X from D.A.V. PUBLIC SCHOOL, Puri underCBSE in2009 with91.2%
EXPERIENCE:
1 Year (7 monthsas Internand5 months as FAE-VLSI) of Wokingexperience atEntuple Technologies
Pvt.Ltd., Bangalore onAnalogCircuitDesign usingCadence Virtuoso.Also,handsonexperience on
ASICdesigntool featuresof Cadence like –INCISIVE,RTLCompilerandEncounter withabilityto
delivertraininginAcademicinstitutions.
TECHNICAL SKILLS:
 ProgrammingLanguages(ScriptingLanguages) : Perl,C,Cadence- Ocean
 Hardware DescriptionLanguage : Verilog
 DesignandSimulationSoftware : CADENCE (Virtuoso-Schematic&Layout,
ENCOUNTER,LIBERATE), PSPICE,SCILAB– XCOS, TINA
PROJECTS:
 Designof OPAMPu741, byrescalingitsspecificationsto CMOSLow Power Technologiesin
GPDK180nm usingCadence bygm/Id methodology
 MOSFET Characterizations inGPDK180nm technologyusingCadence tobuildupaGeneric
Datasheet specifyingall Parametersof MOSFETs
 Designed Mathematical Model (Approximate Model) of Phase LockedLoop -IIusingSCILAB
– XCOS underInternshipatEntuple TechnologiesPvt.Ltd.,Bangalore in2015
 B.TechFinal yearproject-“Designof a Charge Pump in UMC-180nm technologyfor PLL
Applications”in2014
 Temperature and Humiditymeasurementsystem usingARM controllerin 2014
 Graphical User Interface using Java for Robotic Motioncontrol throughRaspberry Pi in
2014
 Quiz BuzzerdesignusingXilinxand implementationon FPGA(Spartan6family)
 WirelesslymonitoredElectronicWaterLevel Indicator withAutomatic Motor Switching
Control in2013
 Designof an IntelligentHome Model - 2012
TRAINING/ WORKSHOPS/SEMINAR:
 Undergone trainingon Characterizationof Standard Cells usingCadence –Liberate
Characterization Tool at Cadence DesignSystems,Bangalore (2daystraining) - 2016
 Undergone trainingon ElectronicDesignAutomation tool for Cadence DesignatNIST-2014
 Undergone trainingon EmbeddedSystemsat NIST– 2014
 Trainedin Electronic DesignAutomationSoftware Tool for VLSI/ASIC Designat NIST– 2013
 QualifiedBusinessEnglishCertificate (BEC) Vantage Level(2nd
Level),Conductedby
UniversityofCambridge – 2012
 AttendedThree Daysworkshopon Eyebotics(Image ProcessingandRobot Application) by
ThinkWare
 Presented Technical Seminaron“Role of Nano-Robots inHuman Body – The Future Scope”
ACHIEVEMENTS:
 Participatedin 4th
IEEE EDS Mini-Colloquiumand1st
National Conference onDevices and
Circuits(NCDC-2015) at NIST- Feb,2015
 QualifiedforQuarter-Final roundof Texas InstrumentsInnovationChallenge,IndiaLevel
Analog DesignContest-2015
 Winnerof ElectronicsDesign Contestheldat NIST,Berhampurin2013
 First runner-upinCollege-Level TexasInstrumentsInnovationChallenge –India Analog
DesignContest-2014 heldatNIST,Berhampur
INTERESTS/ACTIVITIES:
 ElectronicsHardware Design
 Chess
 PlayingComputerGames
 Table Tennis
Date : 5th
May 2016
Place : Bangalore (ParthageetSamantaray)

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Partha's Resume_04052016

  • 1. PARTHAGEETSAMANTARAY S/OMr. PatitapabanSamantaray Ray Bahadur Lane,Balagandi, Puri – 752001 Contact No:+91-8884299705 Odisha Mail ID: pgsmntry@hotmail.com CAREER OBJECTIVE: To acquire a challengingpositionwhere Ican implementmyknowledge andskill andcontributeto organisational growth. EDUCATIONAL QUALIFICATION:  B.Tech in ELECTRONICS AND COMMUNICATIONENGINEERING fromNational Institute of Science and Technology,BerhampurunderBPUT witha CGPA of 8.06  Class XII fromB.JB. JUNIORCOLLEGE, BhubaneswarunderCHSE-OdishaBoardin2011 with 79.5%  CLASS X from D.A.V. PUBLIC SCHOOL, Puri underCBSE in2009 with91.2% EXPERIENCE: 1 Year (7 monthsas Internand5 months as FAE-VLSI) of Wokingexperience atEntuple Technologies Pvt.Ltd., Bangalore onAnalogCircuitDesign usingCadence Virtuoso.Also,handsonexperience on ASICdesigntool featuresof Cadence like –INCISIVE,RTLCompilerandEncounter withabilityto delivertraininginAcademicinstitutions. TECHNICAL SKILLS:  ProgrammingLanguages(ScriptingLanguages) : Perl,C,Cadence- Ocean  Hardware DescriptionLanguage : Verilog  DesignandSimulationSoftware : CADENCE (Virtuoso-Schematic&Layout, ENCOUNTER,LIBERATE), PSPICE,SCILAB– XCOS, TINA PROJECTS:  Designof OPAMPu741, byrescalingitsspecificationsto CMOSLow Power Technologiesin GPDK180nm usingCadence bygm/Id methodology  MOSFET Characterizations inGPDK180nm technologyusingCadence tobuildupaGeneric Datasheet specifyingall Parametersof MOSFETs  Designed Mathematical Model (Approximate Model) of Phase LockedLoop -IIusingSCILAB – XCOS underInternshipatEntuple TechnologiesPvt.Ltd.,Bangalore in2015  B.TechFinal yearproject-“Designof a Charge Pump in UMC-180nm technologyfor PLL Applications”in2014  Temperature and Humiditymeasurementsystem usingARM controllerin 2014  Graphical User Interface using Java for Robotic Motioncontrol throughRaspberry Pi in 2014  Quiz BuzzerdesignusingXilinxand implementationon FPGA(Spartan6family)
  • 2.  WirelesslymonitoredElectronicWaterLevel Indicator withAutomatic Motor Switching Control in2013  Designof an IntelligentHome Model - 2012 TRAINING/ WORKSHOPS/SEMINAR:  Undergone trainingon Characterizationof Standard Cells usingCadence –Liberate Characterization Tool at Cadence DesignSystems,Bangalore (2daystraining) - 2016  Undergone trainingon ElectronicDesignAutomation tool for Cadence DesignatNIST-2014  Undergone trainingon EmbeddedSystemsat NIST– 2014  Trainedin Electronic DesignAutomationSoftware Tool for VLSI/ASIC Designat NIST– 2013  QualifiedBusinessEnglishCertificate (BEC) Vantage Level(2nd Level),Conductedby UniversityofCambridge – 2012  AttendedThree Daysworkshopon Eyebotics(Image ProcessingandRobot Application) by ThinkWare  Presented Technical Seminaron“Role of Nano-Robots inHuman Body – The Future Scope” ACHIEVEMENTS:  Participatedin 4th IEEE EDS Mini-Colloquiumand1st National Conference onDevices and Circuits(NCDC-2015) at NIST- Feb,2015  QualifiedforQuarter-Final roundof Texas InstrumentsInnovationChallenge,IndiaLevel Analog DesignContest-2015  Winnerof ElectronicsDesign Contestheldat NIST,Berhampurin2013  First runner-upinCollege-Level TexasInstrumentsInnovationChallenge –India Analog DesignContest-2014 heldatNIST,Berhampur INTERESTS/ACTIVITIES:  ElectronicsHardware Design  Chess  PlayingComputerGames  Table Tennis Date : 5th May 2016 Place : Bangalore (ParthageetSamantaray)