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RESUMERESUME
NAME: MALLIPUDI MEHER VENKATESH
ADDRESS K-316 LADOSARAI,
SADHANA BOYS HOSTEL,
NEWDELHI, 11030.
Mobile : 8682024148/07836961384
Email : venkateshmeher@gmail.com
OBJECTIVE:
I seek to enhance myself from student level to professional level and prove myself
worthy in the uplift of the working organization.
ACADEMIC PROFILE:
Course Institution University/Board Year Of
Passing
Percentage/Cgpa
M.Tech
(VLSI)
Vellore Institute Of
Technology
VIT University 2015 7.16
B.Tech
(ECE)
Sir C.R.Reddy
College Of
Engineering, Eluru
Andhra
University
2012 69.6%
Intermediate Sri Chaitanya
Junior Kalasala
Intermediate board
of Education
2008 88%
S.S.C St Ann's English
Medium High
School
SSC board of
Education.
2006 82.1%
AREA OF INTEREST:
 ASIC Backend Design, CAD.
 STA Analysis.
TECHNICAL SKILLS:
 CADENCE, MATLAB, MODELSIM.
 SOC ENCOUNTER, Tina Ti, T Spice.
 C, PERL, TCL, VERILOG Programming.
PROJECT’S HANDLED (M.TECH):
1
.
Title : DESIGN AND ASIC IMPLEMENTATION OF PIPELINE PWM
GENERATOR
Duration : 4 MONTHS
Team Size : Three
Description : In this architecture the implemented PWM generation model uses
pipelined and synchronous binary counter which gives the higher
frequencies with lower delays as compared to other PWM methods
with a lower delay. So the speed will be increase.
2
.
Title : VLSI DESIGN OF FEC CODER FOR OFDM
Duration : 4 MONTHS
Team Size : Two
Description : Design of convolution encoder using Modelsim.
3
.
Title : INVERSE CLASS-E RF POWER AMPLIFIER USING FINFET
Duration : 4 MONTHS
Team Size : Three
Description : Drain switching characteristics, output voltage has been found using
T-spice
INDUSTRIAL TRAINING:
 C-DOT, OCB, MDF, BROADBAND COMPONENTS usage and working
functionality at Bharat Sanchar Nigam Limited (BSNL) Kakinada.
CO- CURRICULAR ACTIVITIES:
 Participated in Robotics workshop in ESPARX 2011 at JNTU Kakinada.
 Participated in workshop on VLSI System verification using System Verilog
 Participated in paper presentations conducted by IETE association.
PERSONAL PROFILE:
Gender : male
Date of Birth : 30-07-1990
Religion : Hindu
Nationality : INDIAN
Marital status : Single
LINGUISTIC FLUENCY:
 English
 Telugu
DECLARATION
I here by declare that the above furnished details are fully true to the best of my
knowledge and belief.
Place : Vellore Yours Truly,
Date : 12/07/14 (M.MEHER
VENKATESH)

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mehervenkresume

  • 1. RESUMERESUME NAME: MALLIPUDI MEHER VENKATESH ADDRESS K-316 LADOSARAI, SADHANA BOYS HOSTEL, NEWDELHI, 11030. Mobile : 8682024148/07836961384 Email : venkateshmeher@gmail.com OBJECTIVE: I seek to enhance myself from student level to professional level and prove myself worthy in the uplift of the working organization. ACADEMIC PROFILE: Course Institution University/Board Year Of Passing Percentage/Cgpa M.Tech (VLSI) Vellore Institute Of Technology VIT University 2015 7.16 B.Tech (ECE) Sir C.R.Reddy College Of Engineering, Eluru Andhra University 2012 69.6% Intermediate Sri Chaitanya Junior Kalasala Intermediate board of Education 2008 88% S.S.C St Ann's English Medium High School SSC board of Education. 2006 82.1% AREA OF INTEREST:  ASIC Backend Design, CAD.  STA Analysis. TECHNICAL SKILLS:  CADENCE, MATLAB, MODELSIM.  SOC ENCOUNTER, Tina Ti, T Spice.
  • 2.  C, PERL, TCL, VERILOG Programming. PROJECT’S HANDLED (M.TECH): 1 . Title : DESIGN AND ASIC IMPLEMENTATION OF PIPELINE PWM GENERATOR Duration : 4 MONTHS Team Size : Three Description : In this architecture the implemented PWM generation model uses pipelined and synchronous binary counter which gives the higher frequencies with lower delays as compared to other PWM methods with a lower delay. So the speed will be increase. 2 . Title : VLSI DESIGN OF FEC CODER FOR OFDM Duration : 4 MONTHS Team Size : Two Description : Design of convolution encoder using Modelsim. 3 . Title : INVERSE CLASS-E RF POWER AMPLIFIER USING FINFET Duration : 4 MONTHS Team Size : Three Description : Drain switching characteristics, output voltage has been found using T-spice INDUSTRIAL TRAINING:  C-DOT, OCB, MDF, BROADBAND COMPONENTS usage and working functionality at Bharat Sanchar Nigam Limited (BSNL) Kakinada. CO- CURRICULAR ACTIVITIES:  Participated in Robotics workshop in ESPARX 2011 at JNTU Kakinada.  Participated in workshop on VLSI System verification using System Verilog  Participated in paper presentations conducted by IETE association. PERSONAL PROFILE: Gender : male Date of Birth : 30-07-1990 Religion : Hindu Nationality : INDIAN Marital status : Single
  • 3. LINGUISTIC FLUENCY:  English  Telugu DECLARATION I here by declare that the above furnished details are fully true to the best of my knowledge and belief. Place : Vellore Yours Truly, Date : 12/07/14 (M.MEHER VENKATESH)