Personal Information
Organization / Workplace
Vijayawada Area, India India
Occupation
Physical Verification Engineer at Intel Corporation Pvt Limited
About
M.TECH IN VLSI IN JNTU KAKINADA UNIVERSITY.
Hardware languages : Verilog,system verilog.
Programming Languages : Basics in C.
Scripting languages : Tickle,Perl.
Operating System : Windows,Linux.
EDA Tools : Synopsys VCS , Design Compiler, IC compiler.DFT compiler,Xilinx.
Basic knowledge in STA,ASIC design,Digital Design,Low power techniques,Physical Design,Verification concepts.
Interested in Design and verification, Physical design,DFT.
Tags
verilog
physical design
vlsi
semiconductors
See more
Documents
(1)Personal Information
Organization / Workplace
Vijayawada Area, India India
Occupation
Physical Verification Engineer at Intel Corporation Pvt Limited
About
M.TECH IN VLSI IN JNTU KAKINADA UNIVERSITY.
Hardware languages : Verilog,system verilog.
Programming Languages : Basics in C.
Scripting languages : Tickle,Perl.
Operating System : Windows,Linux.
EDA Tools : Synopsys VCS , Design Compiler, IC compiler.DFT compiler,Xilinx.
Basic knowledge in STA,ASIC design,Digital Design,Low power techniques,Physical Design,Verification concepts.
Interested in Design and verification, Physical design,DFT.
Tags
verilog
physical design
vlsi
semiconductors
See more