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Tmec加工2 151222
1.
分析工房 (株) 有機半導体膜をはじめとしたコーティング薄膜のトランジスタ特性評価を行うためには、ゲー ト、ソース・ドレインの作製プロセスが、通常、必要です。 分析工房では、その煩わしさを解消するために、タイ国立研究所のTMEC(Thai Microelectronics Center)と共同で、ゲート、ソース・ドレインが、あらかじめ作りこまれたチップ をご用意しました。チップの上に有機半導体膜をコーティングするだけでトランジスタとなるの で、その場でトランジスタ特性評価が可能になります。 コーティング薄膜電機評価用チップ 半導体材料のコーテイングだけでトランジスタが完成
2.
分析工房 (株) ソース(メタル) ゲート絶縁膜(2酸化シリコン: 0.6
μm) ドレイン(メタル) ゲート(メタル) 絶縁膜 基板(単結晶シリコン) チャネル長= 28.5 μm チャネル幅= 1.6 mm (ゲート絶縁膜厚は、カスタマイズ可能です) DS G チップ製造: Thai Microelectronics Center
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