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3. Boolean Algebra and Logic Gates 3-1

Chapter 3 Boolean Algebra and Logic
Gates

Algebraic Properties

A set is a collection of objects with a common property.
A binary operator on set Ë is a rule that assigns to each pair of elements in Ë
another unique element in Ë .
The axioms (postulates) of an algebra are the basic assumptions from which
all theorems of the algebra can be proved.
It is assumed that there is an equivalence relation (=), which satisfies the
principle of substitution.
It is reflexive, symmetric, and transitive.
Most common axioms used to formulate an algebra structure (e.g., field):
6 Closure: a set Ë is closed with respect to ¯ if and only if
Ü Ý ¾ Ë ´Ü ¯ Ý µ ¾ Ë .

6 Associativity: a binary operator ¯ on Ë is associative if and only if
Ü Ý Þ ¾ Ë ´Ü ¯ Ý µ ¯ Þ Ü ¯ ´Ý ¯ Þ µ .

6 Identity element: a set Ë has an identity element with respect to ¯ if and
only if ¾ Ë such that Ü ¾ Ë ¯ Ü Ü ¯ Ü .
6 Commutativity: a binary operator ¯ defined on Ë is commutative if and
only if Ü Ý ¾ Ë Ü ¯ Ý Ý ¯ Ü .
6 Inverse element: a set Ë having the identity element with respect to ¯
has an inverse if and only if Ü ¾ Ë Ý ¾ Ë such that Ü ¯ Ý .
6 Distributivity: if ¯ and ¾ are binary operators on Ë , ¯ is distributive over
¾ if and only if Ü Ý Þ ¾ Ë Ü ¯ ´Ý¾Þµ ´Ü ¯ Ýµ¾´Ü ¯ Þµ .

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU
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Axiomatic Definition of Boolean Algebra

Boolean algebra: an algebraic system of logic introduced by George Boole
in 1854.
An Investigation of Laws of Thought on which are Founded the Mathe-
matical Theories of Logic and Probabilities, Macmillan (Dover, 1958)
Switching algebra: a 2-valued Boolean algebra introduced by Claude Shan-
non in 1938.
A Symbolic Analysis of Relay and Switching Circuits, MS Thesis, MIT
Huntington postulates for Boolean algebra: defined on a set with binary
operators + ¡, and the equivalence relation = (Edward Huntington, 1904):
x (a) Closure with respect to +. (b) Closure with respect to ¡.
y (a) Identity element 0 with respect to +. (b) Identity element 1 with
respect to ¡.
z (a) Commutative with respect to +. (b) Commutative with respect to ¡.
{ (a) ¡ is distributive over +. (b) + is distributive over ¡.
| Ü ¾ Ü
¼
¾ (called the complement of Ü) such that (a) Ü · Ü
¼
½
and (b) Ü ¡ Ü
¼
¼.

} There are at least 2 distinct elements in .
The axioms are independent; none can be proved from the others.
Associativity is not included, since it can be derived (for both operators) from
the given axioms.
In ordinary algebra, + is not distributive over ¡.
No additive or multiplicative inverses; no subtraction or division operations.
Complement is not available in ordinary algebra.
is as yet undefined. It is to be defined as the set 0,1 (two-valued Boolean
algebra).
In ordinary algebra, the set Ë can contain an infinite number of elements (e.g.,
all integers).

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Exercise 1
Prove the associative law: ·´ · µ ´ · µ· and ´ µ ´ µ . ¾
B Boolean algebra
6 Set of at least 2 elements (not variables).
6 Rules of operation for the 2 binary operators (+ ¡).
6 Huntington postulates satisfied by the elements of and the operators.
B Two-valued Boolean algebra (switching algebra)
6 ¼ ½ .
6 The binary operations are defined as the logical AND (¡) and OR (+).
For convenience, a unary operation NOT (complement) is also included
when we define the basic operations.
6 The Huntington postulates can be shown valid (read pp. 66-68).
6 Unless otherwise noted, we will use the term Boolean algebra for 2-
valued Boolean algebra.

Basic Theorems of Boolean Algebra
Theorem 1 (Idempotency)
(a) Ü · Ü Ü; (b) Ü ¡ Ü Ü.

Thm. 1(b) is the dual of Thm. 1(a), and vice versa.
Theorem 2
(a) Ü · ½ ½; (b) Ü ¡ ¼ ¼.

Theorem 3 (Absorption)
(a) ÝÜ · Ü Ü; (b) ´Ý · ÜµÜ Ü.
Theorem 4 (Involution)
¼ ¼
´Ü µ Ü.

Theorem 5 (Associativity)
(a) Ü · ´Ý · Þ µ ´Ü · Ý µ · Þ ; (b) Ü´ÝÞ µ ´ÜÝ µÞ .

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Theorem 6 (De Morgan)
(a) ´Ü · Ý µ Ü ¡ Ý ; (b) ´ÜÝ µ · Ý¼.
¼ ¼ ¼ ¼ ¼
Ü

Duality principle: every algebraic expression deducible from the axioms of
Boolean algebra remains valid if · ° ¡ and ½ ° ¼
Theorem 7
If ´Ü½ Ü¾ ÜÒ µ is a Boolean expression of Ò variables, and ´Ü½ Ü¾ Ü Òµ
is its dual expression, then
¼ ¼ ¼ ¼
´Ü½ Ü¾ Ü Òµ ´Ü½ Ü¾ Ü Òµ
Theorem 8 (De Morgan (generalized))

´Ü½ · Ü¾ · ¡¡¡ · Ü Òµ
¼
¡¡¡
¼
Ü½ Ü¾
¼
Ü
¼
Ò
´Ü½Ü¾ ¡¡¡ ÜÒµ
¼ ¼
Ü½ · Ü¾
¼
·¡¡¡ · Ü
¼
Ò

The theorems usually are proved algebraically (i.e., by transformations based
on axioms and theorems) or by truth table.
Exercise 2
Show that the set theory is an example of (multi-element) Boolean algebra. ¾

Boolean Functions
A boolean function is an algebraic expression formed with boolean variables, the
operators OR, AND, and NOT, parentheses, and an equal sign.

When evaluating a boolean function, we must follow a specific order of com-
putation: (1) parenthesis, (2) NOT, (3) AND, and (4) OR.
Any boolean function can be represented by a truth table. The number of
rows in the table is ¾Ò, where Ò is the number of variables in the function.
There are infinitely many algebraic expressions that specify a given boolean
function. It is important to find the simplest one.
Any boolean function can be transformed in a straightforward manner from
an algebraic expression into a logic diagram composed only of AND, OR,
and NOT gates.

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Example 1

¼ ¼
½ ÜÝ · ÜÝ Þ · Ü ÝÞ

¼
Row number Ü Ý Þ ½ ½
0 0 0 0 0 1
1 0 0 1 0 1
2 0 1 0 0 1
3 0 1 1 1 0
4 1 0 0 0 1
5 1 0 1 1 0
6 1 1 0 1 0
7 1 1 1 1 0

¾
A literal is a variable or its complement in a boolean expression, e.g., ½ has
8 literals, 1 OR term (sum term), and 3 AND terms (product terms).
The complement of any function is , which can be obtained by De Mor- ¼

gan’s theorem: 1) take the dual of , and 2) complement each literal in .
Example 2

¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼
½ ´ÜÝ · ÜÝ Þ · Ü ÝÞ µ ´Ü · Ý µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ

¾
x y z x y z

F

F
F
(a) AND−OR expression (b) OR−AND expression

Figure 1: Graphic representation of two expressions for ½ [Gajski].

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Exercise 3
Given Ò variables, how many different boolean functions can we deﬁne? ¾

Algebraic Manipulation

Minimization of the number of literals and the number of terms usually re-
sults in a simpler circuit (less expensive).
The number of literals can be minimized by algebraic manipulation. Unfor-
tunately, there are no speciﬁc rules to follow that will guarantee the optimal
result.
CAD tools for logic minimization are commonly used today.

Some useful rules:

x Ü · Ü¼ Ý Ü ·Ý

y Ü´Ü
¼
· Ýµ ÜÝ

z ÜÝ · ÝÞ · Ü¼ Þ ÜÝ · Ü¼ Þ (the Consensus Theorem I)

{ ´Ü · Ý µ´Ý · Þ µ´Ü¼ · Þ µ ´Ü · Ý µ´Ü¼ · Þ µ (the Consensus Theorem II)

Example 3

¼ ¼ ¼ ¼
ÜÝ · ÜÝ Þ · Ü ÝÞ Ü´Ý · Ý Þ µ · Ü ÝÞ
¼
Ü´Ý · Þ µ · Ü ÝÞ
¼
ÜÝ · ÜÞ · Ü ÝÞ
¼
Ý ´Ü · Ü Þ µ · ÜÞ
Ý ´Ü · Þ µ · ÜÞ
ÜÝ · ÜÞ · ÝÞ

The literal count is reduced from 8 to 6. ¾

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Canonical Forms

2 variables µ 4 combinations (Ü½Ü¾, Ü½Ü¾ , Ü½ Ü¾, and Ü½Ü¾). ¼ ¼ ¼ ¼

Ò variables µ ¾Ò combinations, each is called a minterm (or a standard prod-
uct), denoted as Ñ , ¼ ¾Ò ½. Their complements are called the
maxterms (or standard sums), denoted as Å , ¼ ¾Ò ½.

Canonical forms:
6 Sum-of-minterms (som)
6 Product-of-maxterms (pom)
Each maxterm is the complement of its corresponding minterm: ¼
Ñ Å .

Ü Ý Þ Minterms Notation Maxterms Notation
0 0 0 0 ¼
Ü Ý Þ
¼ ¼
Ñ¼ Ü ·Ý·Þ Å¼
¼ ¼ ¼
1 0 0 1 ÜÝ Þ Ñ½ Ü ·Ý·Þ Å½

2 0 1 0 ¼
Ü ÝÞ
¼
Ñ¾ Ü ·Ý ·Þ
¼
Å¾

3 0 1 1 Ü ÝÞ
¼
Ñ¿ Ü ·Ý ·Þ¼ ¼
Å¿

4 1 0 0 ÜÝ Þ
¼ ¼
Ñ Ü
¼
·Ý·Þ Å

5 1 0 1 ÜÝ Þ
¼
Ñ Ü
¼
·Ý·Þ ¼
Å
¼ ¼ ¼
6 1 1 0 ÜÝÞ Ñ Ü ·Ý ·Þ Å

7 1 1 1 ÜÝÞ Ñ Ü
¼
·Ý ·Þ
¼ ¼
Å

Example 4
Consider the two functions ¾ and ½ as shown in the following table.

¼ ¼
Ü Ý Þ ¾ ¾ ½ ½
0 0 0 0 0 1 0 1
1 0 0 1 1 0 0 1
2 0 1 0 0 1 0 1
3 0 1 1 0 1 1 0
4 1 0 0 1 0 0 1
5 1 0 1 0 1 1 0
6 1 1 0 0 1 1 0
7 1 1 1 1 0 1 0

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Sum-of-minterms:
¼ ¼ ¼ ¼
¾ Ü Ý Þ · ÜÝ Þ · ÜÝÞ Ñ½ ·Ñ ·Ñ ´½ µ
¼ ¼ ¼
½ Ü ÝÞ · ÜÝ Þ · ÜÝÞ · ÜÝÞ Ñ¿ ·Ñ ·Ñ ·Ñ ´¿ µ

Product-of-maxterms:
¼ ¼ ¼ ¼ ¼ ¼ ¼
¾ ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ
Å¼ ¡ Å¾ ¡ Å¿ ¡ Å ¡ Å ´¼ ¾ ¿ µ
¼ ¼ ¼
½ ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ
Å¼ ¡ Å½ ¡ Å¾ ¡ Å ´¼ ½ ¾ µ

Any function can be represented by either of these 2 canonical forms. ¾
To convert from one canonical form to another, interchange
È and É, and list
the numbers that were excluded from the original form.

È´¿ µ is the sum of 1-minterms for
½ ½

¼
È´¼ ½ ¾ µ is the sum of 0-minterms for .
½ ½

How do we convert, e.g., Ü · ÝÞ , into the canonical forms?
By truth table.
By expanding the missing variables in each term, using ½ Ü · ¼
Ü and
¼ Ü ¡Ü .
¼

Exercise 4
Convert Ü Ý
¼ ¼
· ÜÞ to its canonical (som pom) forms. ¾

Standard Forms

Standard forms:
6 Sum-of-products (sop)
6 Product-of-sums (pos)
Product terms (or implicants) are the AND terms, which can have fewer lit-
erals than the minterms.

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Sum terms are the OR terms, which can have fewer literals than the max-
terms.
Standard forms are not unique!
Standard forms can be derived from canonical forms by combining terms that
differ in one variable, i.e., terms with distance 1.
Each product term in the reduced sop form (i.e., no more reduction is possi-
ble) is called a prime implicant (PI).
Each prime implicant represents 1 or more 1-minterms.
Each 1-minterm can be included in several prime implicants.
If there is a 1-minterm included in only 1 prime implicant, then the prime
implicant is an essential prime implicant (EPI).
Each sum term in the reduced pos form is called a prime implicate.
Example 5
¼ ¼ ¼
(a) ½ ÜÝ · ÜÝ Þ · Ü ÝÞ is in sop form, and ½ ´Ü¼ · Ý ¼ µ´Ü¼ · Ý · Þ ¼ µ´Ü · Ý ¼ · Þ ¼ µ
is in pos form.
(b) Consider the boolean function ´ÛÜ · ÝÞ µ´Û Ü
¼ ¼
· ¼
Ý Þ
¼
µ in nonstandard
form.

B Sop form: ¼
Û Ü ÝÞ
¼
· ÛÜÝ ¼ Þ ¼ .

B Pos form: ´Û · Ü¼ µ´Û ¼ · Ý ¼ µ´Ý · Þ ¼ µ´Þ · Üµ. ¾
Nonstandard forms can have fewer literals than standard forms.
Example 6
(a) ÜÝ · ÜÝ Þ · ÜÝ Û
¼ ¼
Ü´Ý · Ý ¼ Þ · Ý ¼ Ûµ Ü´Ý · Ý ¼ ´Þ · Û µµ

(b) ½ ÜÝ · ÜÞ · ÝÞ ÜÝ · ´Ü · Ý µÞ Ü´Ý · Þ µ · ÝÞ ÜÞ · Ý ´Ü · Þ µ ¾

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Other Logic Operations

Ò
There are ¾¾ different boolean functions for Ò binary variables.
There are 16 different boolean functions if Ò ¾.

Table 1: Boolean functions of two variables.

Operator Values ÜÝ Algebraic
Name Symbol 00 01 10 11 Expression Comment
Zero 0 0 0 0 ¼ ¼ Binary constant 0
AND Ü¡Ý 0 0 0 1 ½ ÜÝ Ü and Ý
Inhibition Ü Ý 0 0 1 0 ¾ ÜÝ ¼
Ü but not Ý
Transfer 0 0 1 1 ¿ Ü Ü
Inhibition Ý Ü 0 1 0 0 ÜÝ
¼
Ý but not Ü
Transfer 0 1 0 1 Ý Ý
XOR Ü¨Ý 0 1 1 0 ÜÝ · Ü Ý ¼ ¼
Ü or Ý but not both
OR Ü·Ý 0 1 1 1 Ü·Ý Ü or Ý
NOR Ü Ý 1 0 0 0 ´Ü · Ý µ ¼
Not-OR
Equivalence Ü¬Ý 1 0 0 1 ÜÝ · Ü Ý ¼ ¼
Ü equals Ý
Complement Ý ¼
1 0 1 0 ½¼ Ý ¼
Not Ý
Implication Ü Ý 1 0 1 1 ½½ Ü·Ý ¼
If Ý then Ü
Complement Ü ¼
1 1 0 0 ½¾ Ü ¼
Not Ü
Implication Ü Ý 1 1 0 1 ½¿ Ü ·Ý¼
If Ü then Ý
NAND Ü Ý 1 1 1 0 ½ ´ÜÝ µ ¼
Not-AND
One 1 1 1 1 ½ ½ Binary constant 1

There are 2 functions that generate constants, i.e., the Zero and One functions.
There are 4 functions of one variable which indicate Complement and Trans-
fer operations.
There are 10 functions that deﬁne 8 speciﬁc binary operations: AND, Inhibi-
tion, XOR (exclusive-OR), OR, NOR, Equivalence, Implication and NAND.
Apart from AND, OR, and NOT (complement), the following functions also
are frequently used: NAND, NOR, XOR, XNOR (exclusive-NOR, or equiv-
alence), Transfer.

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Exercise 5
Show that Inhibition and Implication are neither commutative nor associative; and
NAND and NOR are commutative but not associative. Are XOR and XNOR com-
mutative? Are they associative? ¾

Digital Logic Gates

Table 2: Basic logic library in CMOS technology [Gajski].

Name Graphic symbol Function No. transistors Gate delay (ns)
x F
Inverter Ü ¼
2 1
x F
Driver Ü 4 2
x
F
AND y ÜÝ 6 2.4
x
y F
OR Ü·Ý 6 2.4
x
F
NAND y ´ÜÝ µ¼ 4 1.4
x
y F
NOR ´Ü · Ý µ¼ 4 1.4
x
y F
XOR Ü¨Ý 14 4.2
x
y F
XNOR Ü¬Ý 12 3.2

You have to memorize the graphic symbols.
The number of transistors represent the hardware cost. The numbers in this
table are based on the typical complementary metal-oxide semiconductor
(CMOS) implementation.
The gate delay represents the performance. The numbers in this table are also
based on the typical CMOS implementation.
We would like to maximize the performance and minimize the cost.

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Example 7
Consider the full adder as deﬁned in the following truth table.

Ü Ý ·½ ×

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
We ﬁrst derive expressions for the two output functions that contain a minimum
number of operators.

¼ ¼ ¼
·½ Ü Ý ·Ü Ý ·Ü Ý ·Ü Ý
¼ ¼
Ü Ý · ´Ü Ý ·Ü Ý µ
Ü Ý · ´Ü ¨ Ý µ

¼ ¼ ¼ ¼ ¼ ¼
× Ü Ý ·Ü Ý ·Ü Ý ·Ü Ý
¼ ¼ ¼ ¼ ¼
´Ü Ý ·Ü Ý µ · ´Ü Ý ·Ü Ý µ
´Ü ¨ Ý µ ¨
Note that the carry function ·½ could be reduced to Ü Ý · ´Ü · Ý µ.

·½ Ü Ý · ´Ü · Ý µ
¼ ¼ ¼
´´Ü Ý µ ´ ´Ü · Ý µµ µ

× ´Ü ¨ Ý µ
¼
· ´Ü ¬ Ý µ
´Ü ¬ Ý µ ¬
We can implement Ü ¬ Ý with NAND and NOR gates.
Ü ¬ Ý Ü Ý ·Ü
¼
Ý
¼

¼ ¼
´´Ü Ý µ ´Ü · Ý µµ

The gate-level implementations for the full adder are shown in Fig. 2. ¾

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x y
i i

2.4 4.2

c i to c i+1 4.8 ns
c 2.4 2.4 c
i+1 i c to s 4.2 ns
i i
4.2 x ,y to c 9.0 ns
i i i+1
x ,y to si 8.4 ns
i i
si

(a) Design with minimum (b) Input−output delays
number of operators for the design in (a)

x y
i i

1.4 2.4

c 1.4 1.4 c
i+1 i

1.4

1.4 c i to ci+1 2.8 ns
2.4

c i to s i 3.8 ns

1.4 x , y to c i+1 5.2 ns
i i
x i , y to s
i 7.2 ns
i
si

(c) Design with NANDs and ORs (d) Input−output delays
for the design in (c)

Figure 2: Full adder design [Gajski].

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Name Graphic symbol Function No. trs Delay (ns)
x
y F
3-input AND z ÜÝÞ 8 2.8
w
x F
y
4-input AND z ÜÝÞÛ 10 3.2
x
y F
3-input OR z Ü·Ý·Þ 8 2.8
w
x F
y
4-input OR z Ü·Ý·Þ·Û 10 3.2
x
y F
3-input NAND z ´ ÜÝÞ µ ¼
8 1.8
w
x F
y
4-input NAND z ÜÝÞÛµ
´ ¼
10 2.2
x
y F
3-input NOR z ´ Ü · Ý · Þµ ¼
8 1.8
w
x F
y
4-input NOR z ´Ü · Ý · Þ · Ûµ ¼
10 2.2
w
x F
y
2-wide,2-inAOI z ´ÛÜ · ÝÞ µ ¼
8 2.0
u
v
w F
x
y
3-wide,2-inAOI z ´ ÙÚ · ÛÜ · ÝÞ µ ¼
12 2.4
u
v
w F
x
y
2-wide,3-inAOI z ´ÙÚÛ · ÜÝÞ µ ¼
12 2.2
w
x
y F
2-wide,2-inOAI z ´´ Û · Üµ´Ý · Þ µµ ¼
8 2.0
u
v
w F
x
y
3-wide,2-inOAI z ´´ Ù · Úµ´Û · Üµ´Ý · Þ µµ ¼
12 2.2
u
v
w
x F
y
2-wide,3-inOAI z ´´Ù · Ú · Ûµ´Ü · Ý · Þ µµ ¼
12 2.4

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xi
yi
c i to c i+1 3.2 ns
c
i
1.4 1.4 1.4 1.8 1.8 1.8 1.8 c i to si 5.0 ns

x i , y to c
i 3.2 ns
i+1
1.8 2.2 x i , y to si
i 5.0 ns
c i+1 si
(a) Design with multiple−input gates (b) Input−output delays
for the design in (a)

xi
yi
c
i c i to c i+1 3.4 ns

c i to si 4.4 ns
2.0 2.0
2.4
x i , y to c
i+1 3.4 ns
i
1.4 x i , y to s
i 4.4 ns
c i+1 i

si
(a) Design with multiple−operator gates (b) Input−output delays
for the design in (a)

Figure 3: Full adder design using multiple-input and multiple-operator gates [Gajski].

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Gate Implementations
+5V

Î V (Ë closed) µ ÎÓ ¼V
ÎÓ
S Î ¼V (Ë open) µ ÎÓ V
(Î )

Figure 4: Inverter and binary logic.

Positive and negative logic:

Logic type High (3.3V) Low (0V)
Positive logic 1 0
Negative logic 0 1

A A
B . OR 0 1 A B Y V(1)
. Y
N 0 0 1 0 0 0 t
V(0)
1 1 1 0 1 1
· ·¡¡¡·Æ B
1 0 1
A
Y 1 1 1 t
B Y
V

t

Figure 5: OR gate.

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A A
B . AND 0 1 A B Y V(1)
. Y
N 0 0 0 0 0 0 t
V(0)
1 0 1 0 1 0
¡¡¡ Æ B
1 0 0
Y 1 1 1 t
A B
V Y

t

A Y
A Y
0 1
¼
1 0

A
A XOR 0 1 A B Y V(1)
Y
B 0 0 1 0 0 0 t
V(0)
1 1 0 0 1 1
¨ B
1 0 1
1 1 0 t
Y

t

A A B Y A A B Y
Y Y
B 0 0 1 B 0 0 1
0 1 0 0 1 1
´ · µ¼ ´ µ¼
1 0 0 1 0 1
1 1 0 1 1 0

Figure 6: (a) AND gate; (b) NOT gate (Inverter); (c) XOR gate; (d) NOR and NAND gates.

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Negative-logic OR positive-logic AND.
Negative-logic AND positive-logic OR.

Table 3: Examples of positive and negative logic symbols [Gajski].

Positive logic Negative logic

B Noise: undesirable voltage variations that are superimposed on the normal
voltage levels.
B Noise margin: the maximum noise voltage level that can be tolerated by the
gate.

4.0
3.5

3.0
Ouput voltage VO

2.5
2.0
1.5
1.0
0.5

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Input voltage VI

Figure 7: Typical I/O characteristics for an inverter [Gajski].

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VCC (5) VCC (5.0)
H H

VOH (2.4)
High noise
margin VIH (2.0)

Low noise VIL (0.8)
margin
VOL (0.4)
L L

GND (0) GND (0)
Output voltage Input voltage
range range

Figure 8: High and low noise margins [Gajski].

B Fan-out (standard load): the number of gates that each gate can drive, while
providing voltage levels in the guaranteed range.
B The fan-out depends on the amount of current a gate can source or sink while
driving other gates.

IIH IIL

IOH IOL
IIH IIL

IIH IIL

to other gates to other gates
(a) Gate as a current source (b) Gate as a current sink

Figure 9: Current ﬂow in a typical logic circuit [Gajski].

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*Power Dissipation and Propagation Delay

The average power dissipation is the product of average current and power
supply voltage (È Á Î ).
In standard CMOS technology, the power dissipation increases linearly
with respect to the input transition rate.
Heat removal is the major issue for high power dissipation.
Rise time: delay for a signal to switch from 10% to 90% of its nominal value.
Fall time: delay for a signal to switch from 90% to 10% of its nominal value.
Rise time and fall time may not be equal.
ØÈ ÀÄ (ØÈ ÄÀ ): delay for the output signal to reach 50% of its nominal value
on the H-to-L (L-to-H) transition after the input signal reached 50% of its
nominal value.
Propagation delay: ØÈ ´ØÈ ÀÄ · ØÈ ÄÀ µ ¾ .

Rise Fall
time time

90%

Input
50%

10%

90%

Output
50%

10%

tPHL tPLH

Figure 10: Propagation delay [Gajski].

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Integrated Circuits and VLSI Technology

What is an integrated circuit (IC)?

Levels of integration Acronym Number of gates
Small-scale integration SSI 10
Medium-scale integration MSI 10–100
Large-scale integration LSI Hundreds–Thousands
Very large-scale integration VLSI Tens of Thousands
System-on-Chip SOC Millions

Exercise 6
What are the popular digital logic families commonly used today? ¾

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