MARKET TRENDSHistorically, embedded IC package technology is not new at all: several players such as Freescale with its RCP, Infineon with its eWLB and Ibiden for die embedding into PCB laminated substrates have developed dedicated technologies and process IP in this area for years. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs. Things are moving really fast at the moment as this year, we see both Fan-out wafer level packaging and chip embedding into PCB laminate infrastructures emerging at the same time, ramping to high volume production. Fan-Out WLP technology is emerging on both 200mm / 300mm infrastructuresInfineon is having a great sucess with its proprietary eWLB technology: the first FO-WLP wafers are mass produced on 200mm both at Infineon, STATS ChipPAC and ASE since 2009. Indeed, Fan-Out WLP is extending the general concept of Wafer Scale Packaging to new application categories, especially the ones with higher pin-counts and larger chip size such as wireless communication ICs. First embedded package products based on eWLB have been identified within LGE and Nokia handsets. This year, a few additional players are even more aggressive in putting further capacity for eWLB manufacturing as both STATs chippaC and NANIUM are at the moment ramping-up their facilities for manufacturing the first generation eWLB on 300mm reconfigured wafers. Other packaging houses such as SPIL, Amkor, UTAC, ACET and others are also on the point to announce the start of their own Fan-out wafer level packaging operations. Embedded die package technology to expand fast from niche to high volume marketsAt the same time, embedded die package technology has made a lot of progress on its side. Based on PCB laminate infrastructure, chip embedding technology is actually on the way to catch a relatively important portion of the actual WLCSP packaging business as it does leverage the existing WLP/RDL infrastructure already established worldwide: indeed, most of WLCSP die applications are “embedded ready”, so to realize the full benefits of this “WLCSP to Embedded die” conversion, only a few extra manufacturing steps are missing like the realization of thin copper plating process, extreme wafer thinning down to 50ìm, thin dies handling and dicing. Electrical performance, testing and manufacturing yields are still major issues and showstoppers for chip embedding technology to move forward. Therefore, initial volume markets for embedded packages will be rather small, low pin-counts analog type of applications such as integrated passive devices (IPD), RFID and power MOSFET components that are at the moment under qualification for mass production before the end of this year already. Generally speaking, we believe that the winning situation for embedded die packages can be met for company partnerships able to cross-over the traditional packaging, assembly and test supply chain. A good example would be to put together a leading analog IC player (such as TI, Maxim IC, NXP or ST) with a WLP/RDL partner (such as FCI, Casio Micronics, NEPES, etc…) together with a PCB integrator player (such as Imbera / Daeduck, Ibiden, AT&S, Taiyo Yuden or SEMCO). This type of emerging partnerships are absolutely necessary in order to standardize the embedded package technology and to leverage an entire new packaging infrastructure based on low-cost, panel size PCB manufacturing techniques.FOWLP versus Chip Embedding: competing technologies and infrastructures'Today, embedded die and Fan-Out WLP technologies are not competing at all. Indeed, these two emerging semiconductor packaging techniques are targeting very different applications initially: the chip embeddeding technology is looking for replacement of low cost, low pin-counts WLCSP / SOT / QFN / LGA family package applications while FOWLP technology is rather targe

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Embedded Wafer-Level-Packages: Fan-out WLP / Chip Embedding in
Substrate
Published on July 2010
Report Summary
MARKET TRENDS
Historically, embedded IC package technology is not new at all: several players such as Freescale with its RCP, Infineon with its
eWLB and Ibiden for die embedding into PCB laminated substrates have developed dedicated technologies and process IP in this
area for years. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance,
cost reduction and simplification of logistic for OEMs.
Things are moving really fast at the moment as this year, we see both Fan-out wafer level packaging and chip embedding into PCB
laminate infrastructures emerging at the same time, ramping to high volume production.
Fan-Out WLP technology is emerging on both 200mm / 300mm infrastructures
Infineon is having a great sucess with its proprietary eWLB technology: the first FO-WLP wafers are mass produced on 200mm both
at Infineon, STATS ChipPAC and ASE since 2009. Indeed, Fan-Out WLP is extending the general concept of Wafer Scale Packaging
to new application categories, especially the ones with higher pin-counts and larger chip size such as wireless communication ICs.
First embedded package products based on eWLB have been identified within LGE and Nokia handsets. This year, a few additional
players are even more aggressive in putting further capacity for eWLB manufacturing as both STATs chippaC and NANIUM are at the
moment ramping-up their facilities for manufacturing the first generation eWLB on 300mm reconfigured wafers. Other packaging
houses such as SPIL, Amkor, UTAC, ACET and others are also on the point to announce the start of their own Fan-out wafer level
packaging operations.
Embedded die package technology to expand fast from niche to high volume markets
At the same time, embedded die package technology has made a lot of progress on its side. Based on PCB laminate infrastructure,
chip embedding technology is actually on the way to catch a relatively important portion of the actual WLCSP packaging business as
it does leverage the existing WLP/RDL infrastructure already established worldwide: indeed, most of WLCSP die applications are
“embedded ready”, so to realize the full benefits of this “WLCSP to Embedded die” conversion, only a few
extra manufacturing steps are missing like the realization of thin copper plating process, extreme wafer thinning down to 50ìm, thin
dies handling and dicing.
Electrical performance, testing and manufacturing yields are still major issues and showstoppers for chip embedding technology to
move forward. Therefore, initial volume markets for embedded packages will be rather small, low pin-counts analog type of
applications such as integrated passive devices (IPD), RFID and power MOSFET components that are at the moment under
qualification for mass production before the end of this year already. Generally speaking, we believe that the winning situation for
embedded die packages can be met for company partnerships able to cross-over the traditional packaging, assembly and test supply
chain. A good example would be to put together a leading analog IC player (such as TI, Maxim IC, NXP or ST) with a WLP/RDL
partner (such as FCI, Casio Micronics, NEPES, etc…) together with a PCB integrator player (such as Imbera / Daeduck, Ibiden,
AT&S, Taiyo Yuden or SEMCO). This type of emerging partnerships are absolutely necessary in order to standardize the embedded
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package technology and to leverage an entire new packaging infrastructure based on low-cost, panel size PCB manufacturing
techniques.
FOWLP versus Chip Embedding: competing technologies and infrastructures'
Today, embedded die and Fan-Out WLP technologies are not competing at all. Indeed, these two emerging semiconductor packaging
techniques are targeting very different applications initially: the chip embeddeding technology is looking for replacement of low cost,
low pin-counts WLCSP / SOT / QFN / LGA family package applications while FOWLP technology is rather targeting the direct
replacement of higher I/Os (> 120 pins) BGA package applications. However, in the long term, with standardization and through
further technology improvements towards higher yield, better electrical performance, lower profile, better testability and smaller pitch
features, Fan-out WLP and Embedded die technology could seriously compete in the fast growing 3D Packaging market space as
they will both enable the construction of ever more complex, larger SiP modules with different active and passive functions, all
connected on both sides of the active substrate… So Fan-out WLP and chip embeddeding into PCB laminates are just two
additional key pieces of the widening tool-box for 3D Packaging!
COMPANIES CITED IN THE REPORT
3D-Plus, ACET, ADTEC Engineering, Amkor, ams, Analog Devices, AT&S, Aptos, Asahi Glass, ASE, ASM, Atotech, Broadcom,
Bosch, Camtek, Casio Micronics, CIRETEC, CMK, Compass Technology, CSR, Datacon, Daeduck, Denso, Dialog Semiconductor,
Dow Corning, DuPont Electronics, Dyconex, Epic, EVGroup, Fico Molding, Flip-chip International, Fraunhofer IZM, Freescale, Fujitsu,
HD Microsystems, Hynix Semiconductor, Ibiden, Imbera, IME, IMEC, Infineon, ipdia, ITRI, KYEC, Leti, Lintec, LG Electronics, Micron,
MicroChem, Mitsui, Murata, Nagase ChemteX, NANIUM, NEC Electronics, Nitto Denko, Nokia, NSC, NXP, Oki Electric, ORC,
Panasonic, PPT, Qualcomm, Renesas, Rohm & Hass, Rudolph technologies, Samsung, SEMCO, Shinko Electric, SPIL, STATs
chippa C, ST Ericsson, STMicroelectronics, SPTS, SMIC, Shin-Etsu, SÃ'SS Microtec, Taiyo Yuden, TDK , Tessera, Texas
Instruments, tok, Tong Hsing, Toray chemical, Toray Engineering, Toshiba, Towa, Triquint, UMTC, Unimicron, Unovis, UTAC, Vertical
Circuits, Wolfson Microelectronics, Yamada and more…
Table of Content
Scope of the Report & Definitions Objectives of the reportExecutive Summary
1 Embedded die Packaging of active ICs and passive components Motivations and Drivers
Applications & End markets:Status of commercialization Cell phone &
Consumer applications Automotive applications Medical applications 2009 2015 market forecasts for Embedded die packages
In Package shipments (Munits) In Packaging revenues ($M)Supply chain emerging for embedded die packages
Players and positioning in the electronic value chain Who is the most aggressive in the commercialization' Who is doing what:
partnership identifiedTechnology flavors for embedded package Chip first versus chip last' Single die
embedding versus SiP module' SiP multi die integration> Discrete passive integration> Specific features integration (silicon
interposers, holes,fluidic, hermetic cavities, etc…) Challenges related to yield & supply chain Equt & Material Tool Box for
Embedded die Cost structure for Embedded packages manufacturing Comparison with
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competitive package alternative that Embedded die technology is looking for direct replacement (QFN, BGA, WLCSP, SOT,
PoP…) Cost structure target of Embedded die for different application case (RFID, IPD, Power MOSFET / IGBT, DC/DC
converters, PMU, Wireless Connectivity ICs, Digital Baseband, Memories, etc …) Conclusion on “sweets spots” for
the introduction of Embedded die technology in the short / medium / long term
Global Roadmap for Embedded die2 Fan Out WLP package technology development Motivations and
market drivers Thermal performance of FOWLP package compared to FC BGA package solution Applications & status of
commercialization 2009 2015 market forecasts for FOWLP type of packages In Package shipments
(Munits) In Packaging revenues ($M) Supply chain emerging for FOWLP Players and positioning
in the electronic value chain Who is the most aggressive in the commercialization' Who is doing what: partnership identified FOWLP
technologies & challenges Who owns the IP in this space' 1st generation versus 2nd generation
FOWLP TMV “Through Mold Via” fabrication “Panel size” manufacturing for future FO WLP Passive
integration with FO WLP technologies Equipment & Materials for FO WLP Challenges in new
material’s selection and missing equipments Cost structure for FO WLP manufacturing Competitive
package alternative that FOWLP technology is looking for direct replacement (FC CSP, FC BGA, PoP, etc…) Cost structure for
FOWLP by application (RFEM module, PoP digital module, PMU chip, wireless baseband SOC chip, etc…) Conclusion on
“sweets spots” for introduction of FOWLP technology in short / medium long term
Global Roadmap for Fan Out WLPConclusion
Application space for each generation of FO WLP & Embedded die technologyImpact of 3D TSV and silicon interposer technology
conceptsGlobal 3D Packaging development roadmaps mixing interposer, FO WLP and Embedded die package technologies
Appendix Yole Developpement company presentation & services
More Details
COMPANIES CITED IN THE REPORT
3D-Plus, ACET, ADTEC Engineering, Amkor, ams, Analog Devices, AT&S, Aptos, Asahi Glass, ASE, ASM, Atotech, Broadcom,
Bosch, Camtek, Casio Micronics, CIRETEC, CMK, Compass Technology, CSR, Datacon, Daeduck, Denso, Dialog Semiconductor,
Dow Corning, DuPont Electronics, Dyconex, Epic, EVGroup, Fico Molding, Flip-chip International, Fraunhofer IZM, Freescale, Fujitsu,
HD Microsystems, Hynix Semiconductor, Ibiden, Imbera, IME, IMEC, Infineon, ipdia, ITRI, KYEC, Leti, Lintec, LG Electronics, Micron,
MicroChem, Mitsui, Murata, Nagase ChemteX, NANIUM, NEC Electronics, Nitto Denko, Nokia, NSC, NXP, Oki Electric, ORC,
Panasonic, PPT, Qualcomm, Renesas, Rohm & Hass, Rudolph technologies, Samsung, SEMCO, Shinko Electric, SPIL, STATs
chippa C, ST Ericsson, STMicroelectronics, SPTS, SMIC, Shin-Etsu, SÃ'SS Microtec, Taiyo Yuden, TDK , Tessera, Texas
Instruments, tok, Tong Hsing, Toray chemical, Toray Engineering, Toshiba, Towa, Triquint, UMTC, Unimicron, Unovis, UTAC, Vertical
Circuits, Wolfson Microelectronics, Yamada and more…
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