REDA services

Y
Yuri FoninOwner at REDA-Soft
Overview

•   Who we are
•   PPDL- base SoC development
•   HW experience
•   SW experience
•   Partners
REDA: Who we are
 Founded in March 2007…
    … but core team was founded in 2005.
 Core team – 6 persons
     3 – hardware experts, 3 – software experts
Hardware development:
     Analog, digital and mixed-signal IC’s development
     Front-end and back-end development (from specification until
    layout)
    Experience in different technologies:
         180 nm CMOS
         180 nm CMOS + EEPROM
         90 nm CMOS + EEPROM
Embedded and system software development:
     OS kerneldriver development and testing
     Source code optimization for embedded platform
     Tool chain (assembler, simulator, debugger) development
PPDL- base SoC development
REDA: Key service
• Our service:
  – Develop a processor core, co-processor or configurable
    accelerator
  – Full set of HWSW: simulator, synthesizable Verilog,
    assembler, linker, algorithms implementations (for co-
    processor), compiler back-end, binary translators
• Our main advance: PPDL
  –   Is high level architecture description language
  –   Accelerate IP development 3-5 times
  –   Accelerate IP modification 7-15 times
  –   We transfer PPDL license with IP blocks.
  –   You can implement “secret features” of IP yourself, we will
      do only the “common” work.
• Other advances
  – See “Hardware experience”
PPDL: features
                           and evolution
•   Key features
    – One description – several implementations
•   Automatically generated from PPDL:
    – Synthesizable verilog
    – Software simulator:
        • C++ or SystemC
        • Integrated with Sniper (distributed simulator for simulation on clusters)
        • Integrated with GDB or other debuggers
    – Coming soon
        • JIT binary translator (up to 30 MHZ for cycle-accurate model of ARM-like cores)
        • Test suit generator
        • Compiler back-end.
•   PPDL as a service
    – We can provide any generator (XML,CC++).
    – We can provide any language extensions
    – We can provide integration with existent infrastructure.
•   PPDL 2.0 (expected: 06.2013)
    – SIMD as core’s parameter
    – VLIW as core’s parameter
    – Hardware multithreading as parameter
PPDL: Language
                 constructions
• Registers
  – Reg r[16],32,"r[$]";
     • // array of 16 32-bits registers assembly name "r[$]“, ex: “r[1]”
  – Reg FR,16; // 16-bit register
• Flags
  – Flag N,FR[0]; // Flag N is bit 0 of FR
• Memory address spaces (buses)
  – MemSpace data,32,32; // address bus – 32, data bus – 32;
• Lists of arguments
  – ArgList clst,{"N","Z","C,"O"};
  – ArgList RSums,{"r1 + r2","r3 + r4","r5 + r6"}, {r1+r2,
    r3+r4,r5+r6};
PPDL:
              language constructions
• Instruction
  INST "SETF $cidx $sreg",(32,4,cidx=clst,4,sreg=r,24,0xFFFFFF)
  {
    { // decode stage
       sreg.check; // check that the register is not locked
    }
    pa
    { // pipeline stage pa
      tmp = sreg&;
    }
    pb
    {
      FR = tmp & (1<<cidx);
    }
  }
PPDL: service details
• What you became with PPDL:
   – Hardware model with requested characteristics (size, frequency, power
     consumption)
   – Software simulator or JIT compiler
   – Assemblerlinker, optionally compiler back-end.
   – Single PPDL description, from which the all above-mentioned
     components are generated automatically!!!
   – Sufficient test suit
   – PPDL license
   – 1 year support
• With this approach you will can:
   – Adopt the model for your need within a couple of days.
   – Easy configure PPDL models for applications needs
   – Split you task into “common” and “secret” parts, delegate common part
     to us and concentrate into “secret” parts.
   – Be flexible with your IPs !!!
HW-experience
Projects: System–on–chip
IC series for usage in protected identification (ID) systems
• 8/16/32-bit microcontrollers
• Contactless interface corresponding to ISO 14443-2,3,4
  type A/B
• Contact interface acc. ISO 7816
• ROM: 192 – 364 Kbyte
• RAM: 4-6 Kbyte
• EEPROM: 2-72 Kbyte
• Dual Key Triple DES (TDES) encryption accelerator.
• Modular co-processor (up to 1024 bits operands).
• AES encryption acceleration (128, 192 or 256 bits).
Projects: RF-ID
• Contactless interface corresponding to ISO 14443-2,3,4
  type A
• 640 bit – 4 Kbyte EEPROM
• 7-byte UID
• Anti-collision algorithm
• High data integrity during the transmission: 16-bit cyclic
  checksum (CRC), parity, bit coding, bit counting.
• 0.2 mm2 die area (180 nm technology)
• 3DES authentication
Projects: Memories, IP-blocks
-   1Mbit EEPROM with I2C interface
-   4Mbit RAM memory
-   ADC (12-bit, 20 MHz, 1.8 V)
-   I2C interface
-   USB 2.0 High speed interface (in process)
-   640 bit, 1Kbyte, 4Kbyte EEPROM
SW-experience
Hardware simulation
Software modeling experience:
• Functional simulator of NeroMatrix cores NM6403,6405
   – See http://www.module.ru/products/nm.shtml
• Cycle-accurate simulator for NM6405
• Cycle-accurate SDRAM DDRAM simulators
• Correspondent system tools – assembler, tracer, debugger
PC projects
• Universal console tracer
   – Trace and profile simulations for NeroMatrix
   – Supports any simulator is written in PPDL.
   – Supports Linux and Windows

• .Net SystemC Visualization library
   – Visualize SystemC models and edit in graphic mode
   – Library can be easy adopted for any kind of visualization.
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REDA services

  • 1. Overview • Who we are • PPDL- base SoC development • HW experience • SW experience • Partners
  • 2. REDA: Who we are  Founded in March 2007… … but core team was founded in 2005.  Core team – 6 persons  3 – hardware experts, 3 – software experts Hardware development:  Analog, digital and mixed-signal IC’s development  Front-end and back-end development (from specification until layout) Experience in different technologies:  180 nm CMOS  180 nm CMOS + EEPROM  90 nm CMOS + EEPROM Embedded and system software development:  OS kerneldriver development and testing  Source code optimization for embedded platform  Tool chain (assembler, simulator, debugger) development
  • 3. PPDL- base SoC development
  • 4. REDA: Key service • Our service: – Develop a processor core, co-processor or configurable accelerator – Full set of HWSW: simulator, synthesizable Verilog, assembler, linker, algorithms implementations (for co- processor), compiler back-end, binary translators • Our main advance: PPDL – Is high level architecture description language – Accelerate IP development 3-5 times – Accelerate IP modification 7-15 times – We transfer PPDL license with IP blocks. – You can implement “secret features” of IP yourself, we will do only the “common” work. • Other advances – See “Hardware experience”
  • 5. PPDL: features and evolution • Key features – One description – several implementations • Automatically generated from PPDL: – Synthesizable verilog – Software simulator: • C++ or SystemC • Integrated with Sniper (distributed simulator for simulation on clusters) • Integrated with GDB or other debuggers – Coming soon • JIT binary translator (up to 30 MHZ for cycle-accurate model of ARM-like cores) • Test suit generator • Compiler back-end. • PPDL as a service – We can provide any generator (XML,CC++). – We can provide any language extensions – We can provide integration with existent infrastructure. • PPDL 2.0 (expected: 06.2013) – SIMD as core’s parameter – VLIW as core’s parameter – Hardware multithreading as parameter
  • 6. PPDL: Language constructions • Registers – Reg r[16],32,"r[$]"; • // array of 16 32-bits registers assembly name "r[$]“, ex: “r[1]” – Reg FR,16; // 16-bit register • Flags – Flag N,FR[0]; // Flag N is bit 0 of FR • Memory address spaces (buses) – MemSpace data,32,32; // address bus – 32, data bus – 32; • Lists of arguments – ArgList clst,{"N","Z","C,"O"}; – ArgList RSums,{"r1 + r2","r3 + r4","r5 + r6"}, {r1+r2, r3+r4,r5+r6};
  • 7. PPDL: language constructions • Instruction INST "SETF $cidx $sreg",(32,4,cidx=clst,4,sreg=r,24,0xFFFFFF) { { // decode stage sreg.check; // check that the register is not locked } pa { // pipeline stage pa tmp = sreg&; } pb { FR = tmp & (1<<cidx); } }
  • 8. PPDL: service details • What you became with PPDL: – Hardware model with requested characteristics (size, frequency, power consumption) – Software simulator or JIT compiler – Assemblerlinker, optionally compiler back-end. – Single PPDL description, from which the all above-mentioned components are generated automatically!!! – Sufficient test suit – PPDL license – 1 year support • With this approach you will can: – Adopt the model for your need within a couple of days. – Easy configure PPDL models for applications needs – Split you task into “common” and “secret” parts, delegate common part to us and concentrate into “secret” parts. – Be flexible with your IPs !!!
  • 10. Projects: System–on–chip IC series for usage in protected identification (ID) systems • 8/16/32-bit microcontrollers • Contactless interface corresponding to ISO 14443-2,3,4 type A/B • Contact interface acc. ISO 7816 • ROM: 192 – 364 Kbyte • RAM: 4-6 Kbyte • EEPROM: 2-72 Kbyte • Dual Key Triple DES (TDES) encryption accelerator. • Modular co-processor (up to 1024 bits operands). • AES encryption acceleration (128, 192 or 256 bits).
  • 11. Projects: RF-ID • Contactless interface corresponding to ISO 14443-2,3,4 type A • 640 bit – 4 Kbyte EEPROM • 7-byte UID • Anti-collision algorithm • High data integrity during the transmission: 16-bit cyclic checksum (CRC), parity, bit coding, bit counting. • 0.2 mm2 die area (180 nm technology) • 3DES authentication
  • 12. Projects: Memories, IP-blocks - 1Mbit EEPROM with I2C interface - 4Mbit RAM memory - ADC (12-bit, 20 MHz, 1.8 V) - I2C interface - USB 2.0 High speed interface (in process) - 640 bit, 1Kbyte, 4Kbyte EEPROM
  • 14. Hardware simulation Software modeling experience: • Functional simulator of NeroMatrix cores NM6403,6405 – See http://www.module.ru/products/nm.shtml • Cycle-accurate simulator for NM6405 • Cycle-accurate SDRAM DDRAM simulators • Correspondent system tools – assembler, tracer, debugger
  • 15. PC projects • Universal console tracer – Trace and profile simulations for NeroMatrix – Supports any simulator is written in PPDL. – Supports Linux and Windows • .Net SystemC Visualization library – Visualize SystemC models and edit in graphic mode – Library can be easy adopted for any kind of visualization.