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Hardware accelerated Virtualization in the ARM Cortex™ Processors


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Hardware accelerated Virtualization in the ARM Cortex™ Processors

  1. 1. Hardware accelerated Virtualization in the ARM Cortex ™ Processors John Goodacre Director, Program Management ARM Processor Division ARM Ltd. Cambridge UK 2nd November 2010
  2. 2. New Capabilities in the Cortex-A15 <ul><li>Full compatibility with the Cortex-A9 </li></ul><ul><ul><li>Supporting the ARMv7 Architecture </li></ul></ul><ul><li>Addition of Virtualization Extension (VE) </li></ul><ul><ul><li>Run multiple OS binary instances simultaneously </li></ul></ul><ul><ul><li>Isolates multiple work environments and data </li></ul></ul><ul><li>Supporting Large Physical Addressing Extensions (LPAE) </li></ul><ul><ul><li>Ability to use up to 1TB of physical memory </li></ul></ul><ul><li>With AMBA 4 System Coherency (AMBA-ACE) </li></ul><ul><ul><li>Other cached devices can be coherent with processor </li></ul></ul><ul><ul><li>Many core multiprocessor scalability </li></ul></ul><ul><ul><li>Basis of concurrent big.LITTLE Processing </li></ul></ul>
  3. 3. Large Physical Addressing <ul><li>Cortex-A15 introduces 40-bit physical addressing </li></ul><ul><ul><li>Virtual memory (apps and OS) still has 32bit address space </li></ul></ul><ul><li>Offering up to 1 TB of physical address space </li></ul><ul><ul><li>Traditional 32bit ARM devices limited to 4GB </li></ul></ul><ul><li>What does this mean for ARM based systems? </li></ul><ul><ul><li>Reduced address-map congestion </li></ul></ul><ul><ul><li>More applications at the same time </li></ul></ul><ul><ul><li>Multiple resident virtualized operating systems </li></ul></ul><ul><ul><li>Common global physical address in many-core </li></ul></ul>
  4. 4. Virtualization Extensions: The Basics <ul><li>New Non-secure level of privilege to hold Hypervisor </li></ul><ul><ul><li>Hyp mode </li></ul></ul><ul><li>New mechanisms avoid the need Hypervisor intervention for: </li></ul><ul><ul><li>Guest OS Interrupt masking bits </li></ul></ul><ul><ul><li>Guest OS page table management </li></ul></ul><ul><ul><li>Guest OS Device Drivers due to Hypervisor memory relocation </li></ul></ul><ul><ul><li>Guest OS communication with the interrupt controller (GIC) </li></ul></ul><ul><li>New traps into Hyp mode for: </li></ul><ul><ul><li>ID register accesses and idling (WFI/WFE) </li></ul></ul><ul><ul><li>Miscellaneous “difficult” System Control Register cases </li></ul></ul><ul><li>New mechanisms to improve: </li></ul><ul><ul><li>Guest OS Load/Store emulation by the Hypervisor </li></ul></ul><ul><ul><li>Emulation of trapped instructions through syndromes </li></ul></ul>
  5. 5. How does ARM do Virtualization <ul><li>Extensions to the v7-A Architecture, available on the Cortex™-A15 and Cortex-A7 CPUs </li></ul><ul><ul><li>Second stage of address translation (separate page tables) Functionality for virtualizing interrupts inside the Interrupt Controller </li></ul></ul><ul><ul><li>Functionality for virtualizing all CPU features, including CP15 </li></ul></ul><ul><ul><li>Option of a MMU within the system to help virtualize IO </li></ul></ul><ul><li>Hypervisor runs in new “Hyp” exception mode / privilege </li></ul><ul><ul><li>HVC (Hypervisor Call) instruction to enter Hyp mode </li></ul></ul><ul><ul><li>Uses previously unused entry (0X14 offset) in vector table for hypervisor traps </li></ul></ul><ul><ul><li>Hyp mode exception link register, SPSR, stack pointer </li></ul></ul><ul><ul><li>Hypervisor Control Register (HCR) marks virtualized resources </li></ul></ul><ul><ul><li>Hypervisor Syndrome Register (HSR) for Hyp mode entry reason </li></ul></ul>
  6. 6. Virtualization: Third Privilege <ul><li>Guest OS same kernel/user privilege structure </li></ul><ul><li>HYP mode higher privilege than OS kernel level </li></ul><ul><li>VMM controls wide range of OS accesses </li></ul><ul><li>Hardware maintains TZ security (4 th privilege) </li></ul>TrustZone Secure Monitor (Highest Privilege) Secure Apps Secure Operating System Non-secure State Secure State Exceptions Exception Returns User Mode ( Non-privileged ) Supervisor Mode (Privileged) Hyp Mode (More Privileged) Guest Operating System1 App2 App1 Guest Operating System2 App2 App1 Virtual Machine Monitor / Hypervisor 1 2 3
  7. 7. Memory – the Classic Resource <ul><li>Before virtualisation – the OS owns the memory </li></ul><ul><ul><li>Allocates areas of memory to the different applications </li></ul></ul><ul><ul><li>Virtual Memory commonly used in “rich” operating systems </li></ul></ul>Virtual address map of each application Physical Address Map Translations from translation table (owned by the OS)
  8. 8. Virtual Memory in Two Stages Stage 1 translation owned by each Guest OS Virtual address (VA) map of each App on each Guest OS “ Intermediate Physical” address map of each Guest OS (IPA) Physical Address (PA) Map Stage 2 translation owned by the VMM <ul><li>Hardware has 2-stage memory translation </li></ul><ul><li>Tables from Guest OS translate VA to IPA </li></ul><ul><li>Second set of tables from VMM translate IPA to PA </li></ul><ul><li>Allows aborts to be routed to appropriate software layer </li></ul>
  9. 9. Classic Issue: Interrupts <ul><li>An Interrupt might need to be routed to one of: </li></ul><ul><ul><li>Current or different GuestOS </li></ul></ul><ul><ul><li>Hypervisor </li></ul></ul><ul><ul><li>OS/RTOS running in the secure TrustZone environment </li></ul></ul><ul><li>Basic model of the ARM virtualisation extensions: </li></ul><ul><ul><li>Physical interrupts are taken initially in the Hypervisor </li></ul></ul><ul><ul><li>If the Interrupt should go to a GuestOS : </li></ul></ul><ul><ul><ul><li>Hypervisor maps a “virtual” interrupt for that GuestOS </li></ul></ul></ul>Operating System App2 App1 Guest OS 1 App2 App1 Guest OS 2 App2 App1 VMM System without virtualisation System with virtualisation Physical Interrupt Physical Interrupt Virtual Interrupt
  10. 10. Interrupt Virtualization <ul><li>Virtualisation Extensions provides : </li></ul><ul><ul><li>Registers to hold the Virtual Interrupt </li></ul></ul><ul><ul><li>CPSR.{I,A,F} bits in the GuestOS only appling to that OS </li></ul></ul><ul><ul><ul><li>Physical Interrupts are not masked by the CPSR.{I.A.F} bits </li></ul></ul></ul><ul><ul><ul><li>GuestOS changes to I,A,F no longer need to be trapped </li></ul></ul></ul><ul><ul><li>Mechanism to route all physical interrupts to Monitor Mode </li></ul></ul><ul><ul><ul><li>Already utilized in TrustZone technology based devices </li></ul></ul></ul><ul><ul><li>Virtual Interrupts are routed to the Non-secure IRQ/FIQ/Abort </li></ul></ul><ul><ul><li>Guest OS manipulates a virtualized interrupt controller </li></ul></ul><ul><li>Actually available in the Cortex-A9 to aid paravirtualization support for interrupts </li></ul>
  11. 11. Virtual Interrupt Controller <ul><li>New “Virtual” GIC Interface has been Architected </li></ul><ul><ul><li>ISR of GuestOS interacts with the virtual controller </li></ul></ul><ul><ul><li>Pending and Active interrupt lists for each GuestOS </li></ul></ul><ul><ul><li>Interacts with the physical GIC in hardware </li></ul></ul><ul><ul><li>Creates Virtual Interrupts only when priority indicates it is necessary </li></ul></ul><ul><li>GuestOS ISRs therefore do not need calls for: </li></ul><ul><ul><li>Determining interrupt to take [Read of the Interrupt Acknowledge] </li></ul></ul><ul><ul><li>Marking the end of an interrupt [Sending EOI] </li></ul></ul><ul><ul><li>Changing CPU Interrupt Priority Mask [Current Priority] </li></ul></ul>
  12. 12. Virtual GIC <ul><li>GIC now has separate sets of internal registers: </li></ul><ul><ul><li>Physical registers and virtual registers </li></ul></ul><ul><ul><li>Non-virtualized system and hypervisor access the physical registers </li></ul></ul><ul><ul><li>Virtual machines access the virtual registers </li></ul></ul><ul><ul><li>Guest OS functionality does not change when accessing the vGIC </li></ul></ul><ul><li>Virtual registers are remapped by hypervisor so that the Guest OS thinks it is accessing the physical registers </li></ul><ul><ul><li>GIC registers and functionality are identical </li></ul></ul><ul><li>Hypervisor can set IRQs as virtual in the HCR </li></ul><ul><ul><li>Interrupts are configured to generate a Hypervisor trap </li></ul></ul><ul><ul><li>Hypervisor can deliver an interrupt to a CPU running a virtual process using “register lists” of interrupts </li></ul></ul>
  13. 13. Virtual interrupt example <ul><li>External IRQ (configured as virtual by the hypervisor) arrives at the GIC </li></ul><ul><li>GIC Distributor signals a Physical IRQ to the CPU </li></ul><ul><li>CPU takes HYP trap, and Hypervisor reads the interrupt status from the Physical CPU Interface </li></ul><ul><li>Hypervisor makes an entry in register list in the GIC </li></ul><ul><li>GIC Distributor signals a Virtual IRQ to the CPU </li></ul><ul><li>CPU takes an IRQ exception, and Guest OS running on the virtual machine reads the interrupt status from the Virtual CPU Interface </li></ul>Distributor Physical CPU Interface Virtual CPU Interface Virtual IRQ Physical IRQ CPU External Interrupt source Hypervisor Guest OS
  14. 14. Resource Ownership <ul><li>Software-only approaches </li></ul><ul><ul><li>Access to resources by GuestOS intercepted by the VMM </li></ul></ul><ul><ul><ul><li>VMM interprets the GuestOS’s intent </li></ul></ul></ul><ul><ul><ul><li>Provides its own mechanism to meet that intent </li></ul></ul></ul><ul><ul><li>Mechanism of interception varies </li></ul></ul><ul><ul><ul><li>Paravirtualisation adds a hypercall to the source code </li></ul></ul></ul><ul><ul><ul><li>Binary translation adds a hypercall to the binary </li></ul></ul></ul><ul><ul><ul><li>Exceptions in Hardware provide an trapping of operations </li></ul></ul></ul><ul><ul><li>Hypercalls can be more efficient </li></ul></ul><ul><ul><ul><li>More of the intent to be expressed in a single VMM entry </li></ul></ul></ul><ul><li>Hardware assisted approaches: </li></ul><ul><ul><li>Provide further indirection to resources </li></ul></ul><ul><ul><li>Accelerating trapped operations by syndrome information </li></ul></ul>
  15. 15. Helping with Virtual Devices <ul><li>ARM I/O handling uses memory mapped devices </li></ul><ul><ul><li>Reads and Writes to the Device registers have specific side-effects </li></ul></ul><ul><li>Creating “Virtual Devices” requires emulation: </li></ul><ul><ul><li>Typically reads/writes to devices have to trap to the VMM </li></ul></ul><ul><ul><li>VMM interprets the operation and performs emulation </li></ul></ul><ul><ul><li>Perfect virtualization means all possible devices loads/stores emulated </li></ul></ul><ul><ul><li>Fetching and interpreting emulated load/store is performance intensive </li></ul></ul><ul><ul><li>“ Syndrome” information on aborts available for some loads/stores </li></ul></ul><ul><ul><li>Syndrome unpacks key information about the instruction </li></ul></ul><ul><ul><ul><li>Source/Destination register, Size of data transfer, Size of the instruction, SignExtension etc </li></ul></ul></ul><ul><ul><ul><li>If syndrome not available, then fetching of the instruction for emulation still required </li></ul></ul></ul>
  16. 16. Devices and Memory <ul><li>Providing address translation for devices is important </li></ul><ul><ul><li>Allows unmodified device drivers in the GuestOS </li></ul></ul><ul><ul><li>If the device can access memory, GuestOS will program it in IPA </li></ul></ul><ul><li>ARM virtualisation adds option for a “System MMU” </li></ul><ul><ul><li>Enables second stage memory translations in the system </li></ul></ul><ul><li>A System MMU could also provide stage 1 translations </li></ul><ul><ul><li>Allows devices to be programmed into guest’s VA space </li></ul></ul><ul><li>System MMU natural fit for the processor ACP port </li></ul><ul><ul><li>ARM defining a common programming model </li></ul></ul><ul><ul><li>Intent is for the system MMU to be hardware managed using Distributed Virtual Messages found in AMBA 4 ACE </li></ul></ul>
  17. 17. Potential of System MMU
  18. 18. Partitioning in a Secure ARM System <ul><li>ARM TrustZone technology define two worlds </li></ul><ul><ul><li>Everything must live in Normal World or Secure World </li></ul></ul><ul><li>TrustZone-Enhanced processor exports World Information </li></ul><ul><ul><li>Via NS bit (Not Secure) on system bus since AMBA 3 AXI </li></ul></ul><ul><li>TrustZone-Aware devices can partition across both worlds </li></ul><ul><ul><li>Only AMBA AXI compatible devices can be TrustZone-aware </li></ul></ul><ul><li>AMBA 3 AXI Interconnect decodes TZ like an address line </li></ul><ul><li>AMBA AHB and APB do not contain TrustZone information </li></ul><ul><ul><li>AHB and APB devices live in only one World </li></ul></ul><ul><ul><li>Groups of peripherals can be managed from bus interface </li></ul></ul><ul><ul><li>Inclusion of TrustZone Peripheral Controller gives more control </li></ul></ul>
  19. 19. Base Secure System <ul><li>Minimal TrustZone System required for payment solutions </li></ul><ul><ul><li>Protects On-Chip Secure Ram area via TrustZone Memory Adaptor </li></ul></ul><ul><ul><li>Keyboard and screen secured dynamically to protect PIN entry </li></ul></ul><ul><ul><li>Master Key and Random Number Generators for daughter-keys permanently secures. Non-volatile counters required for state management & anti-rollback (fuse based not non-volatile memory due to process geometry limitations) </li></ul></ul>
  20. 20. Extended Secure System <ul><li>Extended TrustZone system enables complex content management </li></ul><ul><ul><li>Builds on Base Secure System </li></ul></ul><ul><ul><li>+ TrustZone ASC to protect media in RAM and off-chip decode </li></ul></ul><ul><ul><li>+ On-chip Crypto, Media Accelerators & DMA Controller for media handling </li></ul></ul>
  21. 21. Propagating System Security NS : N ot S ecure - treated like an address line
  22. 22. Multi-Cluster Virtualization <ul><li>Works just like with a single cluster MPCore system </li></ul><ul><ul><li>Guest OS (like threads) can migrate from CPU to CPU across clusters </li></ul></ul><ul><li>External (virtual) GIC used to handle interrupts </li></ul><ul><ul><li>Functions the same as internal GIC, but accessed by multiple CPUs </li></ul></ul><ul><li>AMBA Coherency Extensions (ACE) </li></ul><ul><ul><li>Manages coherency across clusters </li></ul></ul><ul><li>System MMU allows other bus masters to map from IPA to PA </li></ul><ul><li>Hypervisor needs to be aware of different clusters and CPUs </li></ul><ul><ul><li>But again: it is just like a single cluster system </li></ul></ul><ul><ul><li>Hardware requirements are the same as non-virtualized multi-cluster </li></ul></ul><ul><ul><ul><li>Just make sure there’s enough memory </li></ul></ul></ul>
  23. 23. big.LITTLE Multi-Processing <ul><li>“ Big” processor is paired with a “little” processor </li></ul><ul><ul><li>Processors share exact same ISA and feature set </li></ul></ul><ul><ul><li>High performance tasks run on the Big processor </li></ul></ul><ul><ul><li>Lightweight/non-time-critical tasks run on the little processor </li></ul></ul><ul><ul><li>Best of both worlds solution for high performance and low power </li></ul></ul><ul><li>big.LITTLE Use Models </li></ul><ul><ul><li>big.LITTLE Switch (Swapping) – one CPU cluster active at a time </li></ul></ul><ul><ul><li>big.LITTLE MP – both CPUs can be active, loads dynamically balanced </li></ul></ul>Cortex-A15 Tags SCU L2 Cache Coherent Interconnect Auxiliary Interfaces Tags SCU L2 Kingfisher
  24. 24. System Characteristics of big.LITTLE PERFORMANCE SMS & Voice do not need a 1GHz processor Browser needs full performance for complex rendering but very little if the page is just being read You do not know what combination of apps the user will use, but the Smartphone must continue to be responsive
  25. 25. big.LITTLE Processing <ul><li>Right sized Core for the Right Task </li></ul><ul><ul><li>Cortex-A7 enabled by default with sufficient performance for common usage scenarios </li></ul></ul><ul><ul><li>Cortex-A15 performance for best user experience </li></ul></ul><ul><li>Software alignment allows execution to migrate between cores </li></ul><ul><ul><li>Transparent to user, application and OS </li></ul></ul><ul><li>Optimizes system workload based on application requirements </li></ul><ul><ul><li>Extending existing power management </li></ul></ul><ul><ul><li>Additional benefit though OS Power Management Policy tuning </li></ul></ul><ul><li>End-product delivers longer battery life and richer user experience at the same time </li></ul>
  26. 26. Putting together a big.LITTLE System <ul><li>Cortex-A15 and Cortex-A7 clusters are cache coherent </li></ul><ul><li>CCI-400 maintains cache-coherency between clusters </li></ul><ul><li>GIC-400 provides transparent virtualized Interrupt control </li></ul><ul><li>Supports all big.LITTLE usage models </li></ul>128-bit AMBA 4 CoreLink CCI-400 Cache Coherent Interconnect 128-bit AMBA 4 A7 A15 System Memory GIC-400 Virtual GIC <ul><li>Full task migration (active to active) in less than 20K cycles </li></ul><ul><li>Cache coherency managed </li></ul><ul><li>in hardware </li></ul><ul><li>128-bit system transactions </li></ul><ul><li>Virtualization manager can map OS either across or between clusters </li></ul>Cortex-A15 A15 SCU + L2 Cache Cortex-A7 A7 SCU + L2 Cache
  27. 27. Forms of big.LITTLE <ul><li>big.LITTLE cluster switching </li></ul><ul><ul><li>OS sees big cores or little cores at any one time </li></ul></ul><ul><ul><li>Eases deployment of software on big.LITTLE platforms </li></ul></ul><ul><ul><ul><li>Minimizes OS changes by extending DVFS framework </li></ul></ul></ul><ul><ul><li>Symmetric big/little clusters currently preferred </li></ul></ul><ul><li>Concurrent big.LITTLE </li></ul><ul><li>OS sees all CPUs all the time; better energy and performance matching of compute to workload </li></ul><ul><ul><li>Asymmetric clusters supported </li></ul></ul><ul><ul><li>Expected to be the preferred use model eventually </li></ul></ul><ul><ul><li>Requires OS improvements and changes for efficient operation </li></ul></ul><ul><ul><ul><li>Co-ordination of MP scheduling, power policies, environmental conditions </li></ul></ul></ul>OS Switched L2$ KF KF L2$ A15 A15 L2$ A15 A15 L2$ KF KF OS Spans Clusters
  28. 28. Virtualization and TrustZone <ul><li>TrustZone offers a specialised type of Virtualisation </li></ul><ul><ul><li>Only 2 ‘Worlds’ – not extendable (except through paravirtualization) </li></ul></ul><ul><ul><ul><li>Although VMM can also span both worlds </li></ul></ul></ul><ul><ul><li>Fourth privilege level is provided by CPU’s secure monitor mode </li></ul></ul><ul><ul><li>Non-symmetrical - The two ‘Worlds’ are not equal </li></ul></ul><ul><ul><ul><li>Secure world can access both worlds (33bit addressing) </li></ul></ul></ul>Secure Apps Secure RTOS Secure Monitor Normal World Secure World <ul><li>TrustZone coexists alongside a VMM </li></ul>HARDWARE (Memory, ARM CPU, I/O Devices) Guest Operating System1 App2 App1 (EPG) Guest Operating System2 App2 App1 (Flash ) Virtual Machine Monitor (VMM) or Hypervisor
  29. 29. Spanning Hypervisor Framework SoC Management Domain (ST/TEI) TrustZone Monitor RTOS/uKernel Para-virtualization with platform service API’s Secured hw timer (tick) SoC Management Domains Secured Services Domain Open Platform Hypervisor Full Virtualization (KVM) TZ Monitor Exception Level HYP(ervisor) Exception Level Open OS & Drivers Open OS (Linux) Kernel/Supervisor Exception Level A P P A P P A P P A P P User Exception Level (Application Layer) ARM Non-Secure Execution Environment ARM Secure Execution Environment Resource API Virtualized TZ Call Virtualized TZ Call Resource Driver API NoC sMMU Accelerators (eg DSP / GPU) Virtualized Heterogeneous API Driver (OpenMP RT) Coherence Platform Resources Project website This project in ARM is in part funded by ICT-Virtical, a European project supported under the Seventh Framework Programme (7FP) for research and technological development
  30. 30. Summary <ul><li>Hardware based Virtualization Extensions were introduced in the soon-available Cortex-A15 </li></ul><ul><ul><li>Also found the in the recently announce Cortex-A7 </li></ul></ul><ul><li>Enables full binary compatible virtualization of the CPU </li></ul><ul><ul><li>Supporting both existing and new market scenarios </li></ul></ul><ul><li>Extended into the system and IO through the system MMU </li></ul><ul><li>Independent of the TrustZone environment </li></ul><ul><ul><li>Providing both a secure environment, and a virtualizable non-secured environment </li></ul></ul><ul><li>Software models available now, first silicon 2H2012 </li></ul>

Editor's Notes

  • Key features that are introduced on the Cortex-A15 that have not been seen before: Virtualization – one could do it before through SOFTWARE, but Cortex-A15 brings HARDWARE support making it much more efficient. Large physical addressing – before ARM cores were limited to 4GB of memory. For the most part this is effectively 2-3GB due to address mapping of peripherals etc. Increasing the number of address bits from 32 to 40 enables this increase in usable memory. Note that virtual memory available to a single program is still limited to 32-bit/4GB. AMBA 4 System coherency – allows different clusters of processors or other cached masters to share data efficiently. ARM has supported up to 4xMP previously; AMBA 4 allows MP scale well beyond that. Currently plans include support to 8 and 16 core systems. AMBA 4 can theoretically support more cores than that, but a Cache Coherent Interconnect with more than four ports will need to be created to realize such 16+ core systems. (ARM currently has plans for two and four port CCIs)
  • To do: emphasize what the VMM does. The OS can now manage its own page tables and disable interrupts – details on this later. The VMM can be written to trap all hardware accesses by OS meaning that OS source need not be changed (might want to change it for performance reasons though). For instance, can configure system so that all CP15 register accesses are trapped to Hypervisor mode where they can be handled by VMM. Hyp mode can alias identification registers e.g. CPU ID etc. Interaction between Virtualization and TrustZone is not a subject for now but the two can co-exist and Virtualization is only supported in Non-Secure world.
  • LPAE extensions allows each OS to live in 32-bit virtual address space and VMM to map multiple systems within 40-bit physical address space. The Guest OS believes that IPA is the real PA. The second-stage translation is invisible to it. Without virtualization extensions, VMSAv7 page tables have been extended to allow generation of 40-bit physical addresses at 16MB super-section granularity only. Support of super-sections and 40-bit PA generation is optional in VMSAv7. The LPAE extension (always used for the Stage 2 translation in a virtualized system) allows 4KB granularity over entire 40-bit address range. Support of LPAE without Virtualization is permitted (but not the other way round).
  • ANIMATED Pretty simplified, but still shows delivery of a virtual interrupt. What is missing is the incredibly complex process of the hypervisor restoring the Guest OS context, or deciding which CPU to deliver the virtual interrupt to, or any one of the 101 details that the hypervisor must deal with.
  • We achieve Big-Little system can use the Right-Core for the right task. Built on the coherency and software compatiblity: - Soft ware migration across processors is at a minimal cost This migration is transparent to applications and OS There is a great deal of innovation and differentiation possible here through tuning of OS Power Management, use of Hypervisors and more. [Internal Note: The idea is to rebutt asynchronous DVFS without specifically alluding to it] Even with near-perfect voltage scaling, the “Big” processor cannot match the power and energy efficiency of the simple Kingfisher pipeline for the lower-intensity workloads such as MP3 playback, basic OS UI and communication activity and scrolling Kingfisher establishes a new bar on power-efficient performance for the low and mid-intensity workloads Lead-into next slide: For the more interactive high-intensity workloads Cortex-A15 provides the instantaneous responsiveness. However, for the higher-intensity workloads At the upper end of the spectrum
  • GIC-400 transports interrupts across clusters under hypervisor control
  • Phase I: Single cluster in operation at any given time Good fit for Linux OS estimates system load and invokes performance governors at preset watermarks Governor back end can synchronously call switcher software When performance on one cluster falls below or exceeds required levels, execution switches seamlessly to appropriate cluster Core state switch occurs in sub 20 microseconds OS remains oblivious to state switch OS load estimation re-calculates system capability Virtualizer handles out of bound accesses OS can be built for Cortex-A15 or Kingfisher Switcher handles core switching OS agnostic so easily extended to support other systems Virtualizer natural progression of the switching work Single OS and simultaneous execution across both clusters Switcher layer is redundant – design is consequently simpler Virtualizer continues to handle out-of-bound micro-architectural accesses Dual cluster system appears logically as a single cluster of processors with varying capability Phase II: Native support requires minimal extension to the Linux kernel Machine description for “SMP” platform Inter cluster signaling modifications Map CPUID reference to CPU within target cluster Still about mechanics not policy OS scheduler still won’t make intelligent scheduling decisions Scope for ‘manual’ improvement Forcefully bind threads statically to suitable processor domain Use cgroups and cpusets