# DIGILENT Exercise #1 cise # 1- Digital Circuits and the Nexsys Board G.docx

Jan. 31, 2023
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### DIGILENT Exercise #1 cise # 1- Digital Circuits and the Nexsys Board G.docx

• 1. DIGILENT Exercise #1 cise # 1: Digital Circuits and the Nexsys Board Gate L H H L Name ce AND shapeOR shape A B C a1 a2 Q3 Q4 Q5 Q6 F 01 L L H L HL 03 06 H L H Q5 05 Enter the logic equation for the 3-input circuit above Problem 9: Complete the following A. A pFET turns | ON /OFF ] with LLV and conducts [ LHV / LLV] well (circle one in each bracket) B. An nFET turns [ ON/OFF ] with LLV and conducts [ LHV / LLV] well (circle one in each bracket C. Write the number of transistors used in each gate: NANDORINV AND NOR: Solution problem 9 some concepts: LHV=level high voltage=2/3 V DD to V DD, LLV=low level voltage=0 V to 1/3 V DD * To activate a PFET, there must be a negative voltage with respect to ground at the gate. In practice, connects the terminal supplier PFET channel to a positive voltage source and the drain to a grounded resistor, also the resistance will limit the current flowing through the transistor. The circuit diagram for a PFET has an arrow pointing to the outside of the gate. *the NFET turns on when you apply a positive voltage to the gate terminal. The voltage will be greater than the positive supply voltage whereas the drain terminal, the resistance between the positive terminal and the drain current limiting. For this type of FET, the terminal supplier must be grounded and the schematic symbol for it will have an arrow pointing to the gate of the device. A. A pFET turns ON with LLV and conducts LLV well B. A nFET turns ON with LLV and conduct LHV well. C. nand: 4 (uses 2n transistors to a gate of n inputs); or: 6 (2 inputs) inv:2; and: 6 (2 inputs); nor: 4(uses 2n transistors to a gate of n inputs) ***AND and OR gates can be formed by combining NAND and NOR gates with INV gates***.