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Presentation on ARM Basic

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  1. 1. Presentation on ARM Basics © Copyright 2013, Latest update: June 15, 2013, Call us on : 91-9632839173 E-Mail : E-mail:; Phone : 91-9632839173
  2. 2. Presentation on ARM Basics By : Faizan Ali Khan Mail @ E-mail:; Phone : 91-9632839173
  3. 3. CPU Modes • • • • • • • • • • User mode : The only non-privileged mode. Fast Interrupt mode : A privileged mode that is entered whenever the processor accepts an FIQ interrupt. Interrupt mode: A privileged mode that is entered whenever the processor accepts an IRQ interrupt. Supervisor (svc) mode :A privileged mode entered whenever the CPU is reset or when a SWI instruction is executed. Abort mode : A privileged mode that is entered whenever a prefetch abort or data abort exception occurs. Undefined mode: A privileged mode that is entered whenever an undefined instruction exception occurs. System mode (ARMv4 &above) : The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the CPSR. MON Mode :A monitor mode is introduced to support TrustZone extension in ARM Core. FIQ mode :designed to support a data transfer or channel process or FIQ26 mode: a 26 bit version IRQ mode :used for general purpose interrupt handling or IRQ26 mode: a 26 bit version E-mail:; Phone : 91-9632839173
  4. 4. Registers • Registers R0-R7 are the same across all CPU modes; they are never banked. • R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively. • R13 is also referred to as SP, the Stack Pointer. • R14 is also referred to as LR, the Link Register. • R15 is also referred to as PC, the Program Counter • The PC is a full 32 bits wide, and used singularly as a Program Counter. • The PSR is contained within its own register, the CPSR. • Each privileged mode has a private SPSR register in which to save the CPSR. E-mail:; Phone : 91-9632839173
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  6. 6. ARM Processor Registers E-mail:; Phone : 91-9632839173
  7. 7. Current Program Status Register . • The Current Program Status Register (cpsr) is a dedicated 32-bit register • The condition flags indicates the various conditions that occur while performing arithmetic and logical operations. The various condition flags and their meaning are given in the following table E-mail:; Table 1. Condition Flags Phone : 91-9632839173
  8. 8. Current Program Status Register E-mail:; Phone : 91-9632839173
  9. 9. Current Program Status Register • The allocation of the bits within the CPSR (and the SPSR registers to which it is saved) is: 31 30 29 28 --7 6 4 3 2 1 0 N Z C V I F M4 M3 M2 M1 M0 0 0 0 0 0 User26 mode 0 0 0 0 1 FIQ26 mode 0 0 0 1 0 IRQ26 mode 0 0 0 1 1 SVC26 mode 1 0 0 0 0 User mode 1 0 0 0 1 FIQ mode 1 0 0 1 0 IRQ mode 1 0 0 1 1 SVC mode 1 0 1 1 1 ABT mode 1 1 0 1 1 UND mode E-mail:; Phone : 91-9632839173
  10. 10. Pipelining • Pipeline is used to increase the execution speed • ARM operates only in pipeline mode (3 or 5 pipes). • Any instruction can be divided into different cycles which determine the pipe length. • • • • • For 3 stages pipe (fetch- decode - execute): During fetch, memory is accessed for instruction. During decode, control logic makes control for the execute cycle. During execute, dataflow path is occupied. Without pipelining each instruction will pass by the 3 phases & needs three cycles to execute. • The 3 phases are in most cases un intersecting so while decoding the current instruction a new instruction can be fetched. • It will appear as if the process is executing an instruction in one cycle only due to the usage of pipelining. Thus appears faster. E-mail:; Phone : 91-9632839173
  11. 11. Pipelining • • • • ARM7 has a 3-stage pipeline. ARM9 has a 5-stage pipeline. ARM10 has 6-stage pipeline. ARM11 has 8-stage pipeline. • A simple 3-stage pipeline consists of fetch, decode and execute. • fetch - to fetch the instruction from the code memory indicated by the program counter. • decode - interpret the opcode from the instruction. • execute - based on the opcode, perform required operation on the operand(s). • Latency: time it takes for an instruction to get through the pipeline. • Throughput: number of instructions executed per time period. • Pipelining increases throughput without reducing latency. E-mail:; Phone : 91-9632839173
  12. 12. 3 Stage Pipelining E-mail:; Phone : 91-9632839173
  13. 13. Exception • During the ordinary flow of execution in a user program, the Program Counter usually increases sequentially through the address space, with perhaps a branch here or there to nearby labels, or with branch-and-links to subroutines and functions. • An exception causes this normal flow of execution to be diverted. Exceptions are generated by sources internal or external to the processor. This allows the processor to handle events generated by these sources; such events include:  interrupts generated by some peripheral device,  an attempt to execute an undefined or unimplemented instruction,  a software-generated interrupt, via the swi instruction. • The ARM processor supports seven types of exceptions. When an exception occurs, the processor branches to a fixed address that corresponds to that exception. This fixed address, called the exception vector address, is located in the bottom 32 bytes of the memory map. These 32 bytes are called the exception vector table. E-mail:; Phone : 91-9632839173
  14. 14. ARM Processor Exceptions E-mail:; Phone : 91-9632839173
  15. 15. Handling an Exception • The ARM processor uses the additional (banked) registers associated with each processor mode to help save the processor state. To handle an exception, the ARM processor:  copies the address of the next instruction (the return address), or the return address plus some offset, into the appropriate LR register,  copies the CPSR into the appropriate SPSR,  sets the CPSR mode bits to the processor mode corresponding to the exception,  enforces ARM state by setting bit 5 (the T bit) of CPSR to zero,  possibly disables fast interrupts by setting bit 6 of CPSR to one (only for FIQ exceptions),  disables normal interrupts by setting bit 7 (the I bit) of CPSR to one, and  loads the address of the exception vector into the Program Counter PC. E-mail:; Phone : 91-9632839173
  16. 16. Switching from User Mode to FIQ Mode on a Fast Interrupt Exception E-mail:; Phone : 91-9632839173
  17. 17. Interrupts • A software interrupt is a type of exception that is initiated entirely by software. On the ARM processor, the relevant instruction that does this is swi. When this instruction is executed, it causes the processor to switch into Supervisor mode and branch to the relevant exception vector address, 0x00000008. In other words, swi causes an exception, but one that is foreseen by the program. • Software interrupts are useful because they allow a program running in User mode to switch to a privileged mode; the code that handles the software interrupt can then do whatever is needed on behalf of the user program. An operating system providing input/output routines is a classic example of this. E-mail:; Phone : 91-9632839173
  18. 18. Contd.. • To the ARM processor, swi is just another type of exception. When the processor executes • this instruction, it:  copies the address of the next instruction following the swi into the LR_svc (R14_svc) register. This return address is actually PC – 4; the swi instruction can be found at PC – 8,  copies the CPSR into SPSR_svc (the Supervisor mode SPSR),  sets the CPSR mode bits to Supervisor mode. This has the effect of “swapping in” R13_svc and R14_svc and “swapping out” the previously-visible R13 and R14,  enforces ARM state by setting bit 5 (the T bit) of CPSR to zero,  disables normal interrupts by setting bit 7 (the I bit) of CPSR to one. This means that normal interrupts cannot cause exceptions during the swi call, unless bit 7 is later set to zero in the exception handler’s code. Fast interrupts are not disabled and can still occur;  loads the address of the exception vector, 0x00000008, into the Program Counter PC. • • Once the software interrupt handler has finished its task, it returns control to the calling program by: 1. moving the contents of register LR_svc (R14_svc) into PC, and 2. copying SPSR back to CPSR. The following single instruction performs both of these steps: movs pc, lr ; Copy current LR to PC and copy current SPSR to CPSR E-mail:; Phone : 91-9632839173
  19. 19. Interrupt vector table • A table of interrupt vectors (pointers to routines that handle interrupts). • On PCs, the interrupt vector table consists of 256 4-byte pointers, and resides in the first 1 K of addressable memory. • Each interrupt number is reserved for a specific purpose. For example, 16 of the vectors are reserved for the 16 IRQ (interrupt request) lines. • An interrupt vector table is also called a dispatch table. • An interrupt vector table is used in all 3 of the 3 most popular methods of finding the starting address of the interrupt service routine E-mail:; Phone : 91-9632839173
  20. 20. Interrupt vector table E-mail:; Phone : 91-9632839173
  21. 21. ARM Architecture Revisions E-mail:; Phone : 91-9632839173
  22. 22. ARM Nomenclature • The letters and numbers after the word “ARM” indicate the features a processor may have. • All ARM cores after the ARM7TDMI include the TDMI features even though they may not include those letters after the “ARM” label. • The processor family is a group of processor implementations that share the same hardware characteristics. For example, the ARM7TDMI, ARM740T, and ARM720T all share the same family characteristics and belong to the ARM7 family. • JTAG is described by IEEE 1149.1 Standard Test Access Port and boundary scan architecture. It is a serial protocol used by ARM to send and receive debug information between the processor core and test equipment. • Embedded ICE macrocell is the debug hardware built into the processor that allows breakpoints and watchpoints to be set. • Synthesizable means that the processor core is supplied as source code that can be compiled into a form easily used by EDA tools. E-mail:; Phone : 91-9632839173
  23. 23. ARM Processor Families • ARM has designed a number of processors that are grouped into different families according to the core they use. The families are based on the ARM7, ARM9, ARM10, and ARM11 cores. • The postfix numbers 7, 9, 10, and 11 indicate different core designs. The ascending number equates to an increase in performance and sophistication. ARM8 was developed but was soon superseded. • An ARM processor comprises a core plus the surrounding components that interface it with a bus. • The core extensions include the following:  Caches are used to improve the overall system performance.  TCMs are used to improve deterministic real-time response. E-mail:; Phone : 91-9632839173
  24. 24. ARM Processor Families E-mail:; Phone : 91-9632839173
  25. 25. ARM Instruction Sets E-mail:; Phone : 91-9632839173
  26. 26. ARM Instruction Format • Each instruction is encoded into a 32-bit word Access to memory is provided only by Load and Store instructions • The basic encoding format for the instructions, such as Load, Store, Move, Arithmetic, and Logic instructions, is shown below • An instruction specifies a conditional execution code (Condition), the OP code, two or three registers (Rn, Rd, and Rm), and some other information E-mail:; Phone : 91-9632839173
  27. 27. Conditional Execution of Instructions • A distinctive and somewhat unusual feature of ARM processors is that all instructions are conditionally executed • Depending on a condition specified in the instruction The instruction is executed only if the current state of the processor condition code flag satisfies the condition specified in bits b31-b28 of the instruction • Thus the instructions whose condition is not meet the processor condition code flag are not executed • One of the conditions is used to indicate that the instruction is always executed E-mail:; Phone : 91-9632839173
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  30. 30. Using and updating the Condition Field • To execute an instruction conditionally, simply postfix it with the appropriate condition: • For example an add instruction takes the form: ADD r0,r1,r2; r0 = r1 + r2 (ADDAL) • To execute only if the zero flag is set: ADDEQ r0,r1,r2; If zero flag set then…; ... r0 = r1 + r2 • By default, data processing operations do not affect the condition flags (apart from the comparisons where this is the only effect). To cause the condition flags to be updated, the S bit of the instruction needs to be set by postfixing the instruction (and any condition code) with an “S”. • For example to add two numbers and set the condition flags: ADDS r0,r1,r2; r0 = r1 + r2 ; ... and set flags E-mail:; Phone : 91-9632839173
  31. 31. Memory Addressing Modes • Pre-indexed mode • The effective address of the operand is the sum of the contents of the base register Rn and an offset value • Pre-indexed with writeback mode • The effective address of the operand is generated in the same way as in the Pre-indexed mode, and then the effective address is written back into Rn • Post-indexed mode • The effective address of the operand is the contents of Rn. The offset is then added to this address and the result is written back into Rn E-mail:; Phone : 91-9632839173
  32. 32. Data processing Instructions • Largest family of ARM instructions, all share the same instruction format. • It Contains : Arithmetic operations Comparisons (no results ‐just set condition codes) Logical operations Data movement between registers • These instruction only work on registers, NOT memory. • They each perform a specific operation on one or two operands. First operand is always a register ‐Rn • Second operand is sent to the ALU via barrel shifter. E-mail:; Phone : 91-9632839173
  33. 33. Arithmetic Instructions • • The basic expression for arithmetic instructions is OPcode Rd, Rn, Rm For example, ADD R0, R2, R4 Performs the operation R0[R2]+[R4] SUB R0, R6, R5 Performs the operation R0[R6]-[R5] • • • Immediate mode: ADD R0, R3, #17 Performs the operation R0[R3]+17 • • • The second operand can be shifted or rotated before being used in the operation For example, ADD R0, R1, R5, LSL #4 operates as follows: the second operand stored in R5 is shifted left 4-bit positions (equivalent to [R5]x16), and its is then added to the contents of R1; the sum is placed in R0 • • E-mail:; Phone : 91-9632839173
  34. 34. Arithmetic Instructions • • • • • • • Operations are: ADD ADC SUB SBC RSB RSC • Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 • Examples ADD r0, r1, r2 SUBGT r3, r3, #1 RSBLES r4, r5, #5 operand1 + operand2; operand1 + operand2 + carry; operand1 ‐operand2; operand1 ‐operand2 + carry ‐1 ; operand2 ‐operand1; operand2 ‐operand1 + carry ‐1; E-mail:; Add Add with carry Subtract Subtract with carry Reverse subtract Reverse subtract with carry Phone : 91-9632839173
  35. 35. Multiplication Instructions • The Basic ARM provides two multiplication instructions. • Multiply MUL{<cond>}{S} Rd, Rm, Rs; Rd = Rm * Rs • Multiply Accumulate‐does addition for free MLA{<cond>}{S} Rd, Rm, Rs,Rn; Rd = (Rm * Rs) + Rn • Restrictions on use: • Rd and Rm cannot be the same registerCan be avoided by swapping Rm and Rs around. This works because multiplication is commutative. E-mail:; Phone : 91-9632839173
  36. 36. Logic Instructions • The logic operations AND, OR, XOR, and Bit-Clear are implemented by instructions with the OP codes AND, ORR, EOR, and BIC. • For example • AND R0, R0, R1: performs R0[R0]+[R1] • The Bit-Clear instruction (BIC) is closely related to the AND instruction. • It complements each bit in operand Rm before ANDing them with the bits in register Rn. • For example, BIC R0, R0, R1. Let R0=02FA62CA, R1=0000FFFF. Then the instruction results in the pattern 02FA0000 being placed in R0. • The Move Negative instruction complements the bits of the source operand and places the result in Rd. • For example, MVN R0, R3 E-mail:; Phone : 91-9632839173
  37. 37. Logical Operations • • • • • • Operations are: AND EOR ORR ORN BIC • Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 • Examples: ANDr0, r1, r2 BICEQr2, r3, #7 EORSr1,r3,r0 operand1 AND operand2 operand1 EOR operand2 operand1 OR operand2 operand1 NOR operand2 operand1 AND NOT operand2 [ie bit clear] E-mail:; Phone : 91-9632839173
  38. 38. Branch Instructions • Conditional branch instructions contain a signed 24-bit offset that is added to the updated contents of the Program Counter to generate the branch target address • Offset is a signed 24-bit number. It is shifted left two-bit positions (all branch targets are aligned word addresses), signed extended to 32 bits, and added to the updated PC to generate the branch target address • The updated points to the instruction that is two words (8 bytes) forward from the branch instruction • The format for the branch instructions is shown as below E-mail:; Phone : 91-9632839173
  39. 39. Conditional Branches E-mail:; Phone : 91-9632839173
  40. 40. Comparisons • • • • • • The only effect of the comparisons is to update the condition flags. Thus no need to set S bit. Operations are: CMP operand1 ‐operand2; Compare CMN operand1 + operand2; Compare negative TST operand1 AND operand2; Test TEQ operand1 EOR operand2; Test equivalence • Syntax: <Operation>{<cond>} Rn, Operand2 • Examples: CMP r0, r1 TSTEQ r2, #5 E-mail:; Phone : 91-9632839173
  41. 41. The Barrel Shifter • The ARM doesn’t have actual shift instructions. • Instead it has a barrel shifter which provides a mechanism to carry out shifts as part of other instructions. • Left Shift • Shifts left by the specified amount (multiplies by powers of two) • Example LSL #5 => multiply by 32 E-mail:; Phone : 91-9632839173
  42. 42. Barrel Shifter ‐Right Shifts E-mail:; Phone : 91-9632839173
  43. 43. Barrel Shifter ‐Rotations E-mail:; Phone : 91-9632839173
  44. 44. Thank You © Copyright 2013, Latest update: Janl 30, 2013, Call us on : 91-9632839173 E-Mail : E-mail:; Phone : 91-9632839173